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* | Added "test_cell -nosat"Clifford Wolf2014-09-071-59/+73
* | Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-064-4/+5
* | Added $macc eval modelClifford Wolf2014-09-061-0/+22
* | Added $macc SAT modelClifford Wolf2014-09-064-11/+83
* | Fixed $clog2 (off by one error)Clifford Wolf2014-09-061-2/+2
* | Added $macc simlib model (also use as techmap rule for now)Clifford Wolf2014-09-062-0/+172
* | Fixed assignment of out-of bounds array elementClifford Wolf2014-09-061-2/+26
* | Added $macc cell typeClifford Wolf2014-09-064-9/+242
* | Fixed autotest for non-basename argumentsClifford Wolf2014-09-061-0/+3
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-09-0625-39/+107
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| * \ Merge pull request #38 from rubund/masterClifford Wolf2014-09-0622-39/+39
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| | * | Corrected spelling mistakes found by lintianRuben Undheim2014-09-0622-39/+39
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| * | Added tests/various/constmsk_test.ysClifford Wolf2014-09-043-0/+68
* | | Added "test_cell -script"Clifford Wolf2014-09-061-1/+8
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* | Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-041-9/+4
* | Removed $bu0 cell typeClifford Wolf2014-09-0418-103/+27
* | Using $pos models for $bu0Clifford Wolf2014-09-033-18/+3
* | Fixed "test_cells -vlog"Clifford Wolf2014-09-031-4/+6
* | Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-032-6/+5
* | Undef-related fixes in simlib $alu modelClifford Wolf2014-09-021-3/+6
* | Improvements in "test_cell -vlog"Clifford Wolf2014-09-021-3/+8
* | Added test_cell -vlogClifford Wolf2014-09-021-2/+79
* | Create a default selection stack in RTLIL::Design::Design()Clifford Wolf2014-09-022-2/+1
* | Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-023-9/+8
* | Added SAT testing to test_cell eval stageClifford Wolf2014-09-021-1/+89
* | Removed references to yosys-svgviewer from docsClifford Wolf2014-09-024-24/+12
* | Removed yosys-svgviewerClifford Wolf2014-09-0214-1121/+18
* | Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-022-5/+4
* | Added $alu support to test_cellClifford Wolf2014-09-011-1/+22
* | Added ConstEval model for $alu cellsClifford Wolf2014-09-011-0/+56
* | Added SAT model for $alu cellsClifford Wolf2014-09-011-2/+69
* | Fixed "test_cell -simlib all"Clifford Wolf2014-09-011-2/+3
* | Added "test_cell -simlib -v"Clifford Wolf2014-09-011-8/+29
* | Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
* | Fixes in old SAT example.ysClifford Wolf2014-09-011-3/+4
* | Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-015-2/+2
* | Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-014-38/+35
* | Added eval testing to test_cellClifford Wolf2014-08-311-0/+88
* | Fixed return size of const_*() eval functionsClifford Wolf2014-08-311-1/+5
* | Added RTLIL::Const::size()Clifford Wolf2014-08-311-0/+2
* | Added eval model for $lut cellsClifford Wolf2014-08-311-0/+26
* | Typo fixes in cell->*Param() APIClifford Wolf2014-08-311-4/+4
* | Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-314-9/+102
* | Added design->scratchpadClifford Wolf2014-08-3010-64/+91
* | Added $alu cell typeClifford Wolf2014-08-305-3/+67
* | Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-303-4/+6
* | Improved write address decoder generation memory_mapClifford Wolf2014-08-301-16/+28
* | Fixed module->addPmux()Clifford Wolf2014-08-301-1/+0
* | Using worker class in memory_mapClifford Wolf2014-08-301-226/+231
* | Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-301-32/+28
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