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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-02 14:26:15 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-02 14:26:15 +0100 |
| commit | 3818e1160dae272b56692a86b6b0b55159a359a8 (patch) | |
| tree | a33e3f6f01049a709b61aecd17e8e7f5097ecf32 | |
| parent | 4a38d15f0df29a2ea62188432678274c84a89c73 (diff) | |
| download | yosys-3818e1160dae272b56692a86b6b0b55159a359a8.tar.gz yosys-3818e1160dae272b56692a86b6b0b55159a359a8.tar.bz2 yosys-3818e1160dae272b56692a86b6b0b55159a359a8.zip | |
Update CHANGELOG
| -rw-r--r-- | CHANGELOG | 12 |
1 files changed, 12 insertions, 0 deletions
@@ -5,6 +5,11 @@ List of major changes and improvements between releases Yosys 0.14 .. Yosys 0.14-dev -------------------------- + * Various + - clk2fflogic: nice names for autogenerated signals + - simulation include support for all flip-flop types. + - Added AIGER witness file co-simulation. + * Verilog - Fixed evaluation of constant functions with variables or arguments with reversed dimensions @@ -14,6 +19,13 @@ Yosys 0.14 .. Yosys 0.14-dev * SystemVerilog - Added support for accessing whole sub-structures in expressions + + * New commands and options + - Added glift command, used to create gate-level information flow tracking + (GLIFT) models by the "constructive mapping" approach + + * Verific support + - Ability to override default parser mode for verific -f command. Yosys 0.13 .. Yosys 0.14 -------------------------- |