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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-11 15:11:14 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-11 15:11:14 +0100 |
| commit | b72c779204120d53895d895d3599b4c87fc2f687 (patch) | |
| tree | d70e0d7d337541900020696c099b20152b70d7ee | |
| parent | d340f302f6255b6aedcf8351a6374b34889edbbc (diff) | |
| download | yosys-b72c779204120d53895d895d3599b4c87fc2f687.tar.gz yosys-b72c779204120d53895d895d3599b4c87fc2f687.tar.bz2 yosys-b72c779204120d53895d895d3599b4c87fc2f687.zip | |
Support cell name in btor witness file
| -rw-r--r-- | passes/sat/sim.cc | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index e49f895f7..5d8e44830 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1290,12 +1290,21 @@ struct SimWorker : SimShared RTLIL::IdString escaped_s = RTLIL::escape_id(signal_name(parts[len-1])); if (len==3) { Wire *w = topmod->wire(escaped_s); - if (!w) - log_warning("Wire %s not present in module %s\n",log_id(escaped_s),log_id(topmod)); - if (w && (int)parts[1].size() != w->width) - log_error("Size of wire %s is different than provided data.\n", log_signal(w)); - if (w) + if (!w) { + Cell *c = topmod->cell(escaped_s); + if (!c) + log_warning("Wire/cell %s not present in module %s\n",log_id(escaped_s),log_id(topmod)); + else if (c->type.in(ID($anyconst), ID($anyseq))) { + SigSpec sig_y= c->getPort(ID::Y); + if ((int)parts[1].size() != GetSize(sig_y)) + log_error("Size of wire %s is different than provided data.\n", log_signal(sig_y)); + top->set_state(sig_y, Const::from_string(parts[1])); + } + } else { + if ((int)parts[1].size() != w->width) + log_error("Size of wire %s is different than provided data.\n", log_signal(w)); top->set_state(w, Const::from_string(parts[1])); + } } else { Cell *c = topmod->cell(escaped_s); if (!c) |