| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 |
| * | Extend test with renaming cells with prefix too | Eddie Hung | 2019-10-02 | 1 | -0/+2 |
| * | Add test | Eddie Hung | 2019-09-30 | 1 | -0/+16 |
| * | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 |
| * | Fix typo | Eddie Hung | 2019-09-30 | 1 | -1/+1 |
| * | Update doc for equiv_opt | Eddie Hung | 2019-09-30 | 1 | -2/+3 |
| * | Merge pull request #1406 from whitequark/connect_rpc | whitequark | 2019-09-30 | 11 | -0/+1767 |
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| | * | rpc: new frontend. | whitequark | 2019-09-30 | 9 | -0/+744 |
| | * | libs: import json11. | whitequark | 2019-09-30 | 3 | -0/+1023 |
| * | | Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors | Eddie Hung | 2019-09-30 | 1 | -0/+2 |
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| | * | | Generate Python wrappers for inline constructors | Benedikt Tutzer | 2019-09-23 | 1 | -0/+2 |
| * | | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 4 | -6/+10 |
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| | * | | | Fix reading aig files on windows | Miodrag Milanovic | 2019-09-29 | 1 | -1/+5 |
| | * | | | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 4 | -5/+5 |
| * | | | | Bump version | Clifford Wolf | 2019-09-30 | 1 | -1/+1 |
| * | | | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+2 |
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| | * | | | | equiv_opt to call async2sync when not -multiclock like SymbiYosys | Eddie Hung | 2019-09-27 | 1 | -0/+2 |
| * | | | | | Merge pull request #1417 from YosysHQ/clifford/fixasync2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+1 |
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| | * | | | | | Fix $dlatch handling in async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+1 |
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| * | | | | | Add latch test modified from #1363 | Eddie Hung | 2019-09-30 | 2 | -0/+73 |
| * | | | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 |
| * | | | | | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 3 | -2/+77 |
| * | | | | | Merge pull request #1414 from hzeller/improve-replace-with-empty-map | Eddie Hung | 2019-09-29 | 1 | -0/+2 |
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| | * | | | | | Avoid work in replace() if rules empty. | Henner Zeller | 2019-09-29 | 1 | -0/+2 |
| * | | | | | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 44 | -281/+6234 |
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| | * | | | | | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 |
| | * | | | | | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | * | | | | | Ooops AREG and BREG to default to -1 | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | * | | | | | Update doc with max cascade chain of 20 | Eddie Hung | 2019-09-26 | 1 | -2/+4 |
| | * | | | | | Do not always zero out C (e.g. during cascade breaks) | Eddie Hung | 2019-09-26 | 2 | -7/+3 |
| | * | | | | | Update doc | Eddie Hung | 2019-09-26 | 1 | -1/+2 |
| | * | | | | | Zero out ports | Eddie Hung | 2019-09-26 | 1 | -2/+2 |
| | * | | | | | xilinx_dsp_cascade to also cascade AREG and BREG | Eddie Hung | 2019-09-26 | 2 | -454/+172 |
| | * | | | | | Try recursive pmgen for P cascade | Eddie Hung | 2019-09-26 | 1 | -88/+118 |
| | * | | | | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 |
| | * | | | | | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
| | * | | | | | CREG to check for \keep | Eddie Hung | 2019-09-26 | 1 | -0/+3 |
| | * | | | | | Remove newline | Eddie Hung | 2019-09-26 | 1 | -1/+0 |
| | * | | | | | select once | Eddie Hung | 2019-09-26 | 2 | -8/+12 |
| | * | | | | | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 3 | -38/+14 |
| | * | | | | | mul2dsp.v slice names | Eddie Hung | 2019-09-25 | 1 | -5/+5 |
| | * | | | | | Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed) | Eddie Hung | 2019-09-25 | 1 | -1/+5 |
| | * | | | | | Reject if (* init *) present | Eddie Hung | 2019-09-25 | 2 | -0/+6 |
| | * | | | | | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit | Eddie Hung | 2019-09-25 | 1 | -3/+1 |
| | * | | | | | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" | Eddie Hung | 2019-09-25 | 1 | -2/+6 |
| | * | | | | | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | * | | | | | Rework xilinx_dsp postAdd for new wreduce call | Eddie Hung | 2019-09-25 | 1 | -3/+3 |
| | * | | | | | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
| | * | | | | | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 |
| | * | | | | | Fix memory issue since SigSpec& could be invalidated | Eddie Hung | 2019-09-25 | 1 | -6/+10 |
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index : iCE40/yosys | |
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