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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 17:26:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 17:26:47 -0700 |
| commit | 34aa3532fb1df2300da83df4071b46da69e3723c (patch) | |
| tree | 618199c0ba1de1e3a0450b3ac1433b68acd273ac | |
| parent | a4238637acc4e6670ccefb1894b00c602a827408 (diff) | |
| download | yosys-34aa3532fb1df2300da83df4071b46da69e3723c.tar.gz yosys-34aa3532fb1df2300da83df4071b46da69e3723c.tar.bz2 yosys-34aa3532fb1df2300da83df4071b46da69e3723c.zip | |
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
| -rw-r--r-- | techlibs/common/mul2dsp.v | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index 3ca69b7b1..9932e288f 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -77,10 +77,8 @@ module _80_mul (A, B, Y); else if (Y_WIDTH < `DSP_Y_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
- else if (_TECHMAP_CELLTYPE_ == "$mul" && A_SIGNED != B_SIGNED)
- wire _TECHMAP_FAIL_ = 1;
`ifdef DSP_SIGNEDONLY
- else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED)
+ else if (_TECHMAP_CELLTYPE_ == "$mul" && !A_SIGNED && !B_SIGNED)
\$mul #(
.A_SIGNED(1),
.B_SIGNED(1),
|