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* Make SV2017 compliant courtesy of @wsnyderEddie Hung2019-12-121-3/+1
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* Update README.md :: abc_ -> abc9_Eddie Hung2019-12-111-3/+3
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* Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
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* Merge pull request #1564 from ZirconiumX/intel_housekeepingDavid Shah2019-12-118-6/+6
|\ | | | | Intel housekeeping
| * synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
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| * synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
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* | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-098-51/+225
|\ \ | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
| * | ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
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| * | ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
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| * | unmap $__ICE40_CARRY_WRAPPER in testEddie Hung2019-12-091-1/+21
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| * | -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
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| * | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-092-8/+12
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| * | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-094-39/+61
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| * | Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-062-2/+10
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| * | Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
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| * | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+30
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| * | Check SB_CARRY name also preservedEddie Hung2019-12-031-0/+1
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| * | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
| | | | | | | | | | | | name and attr
| * | ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
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| * | ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
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| * | Add testcaseEddie Hung2019-12-031-0/+60
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* | | Merge pull request #1555 from antmicro/fix-macc-xilinx-testEddie Hung2019-12-061-1/+1
|\ \ \ | | | | | | | | tests: arch: xilinx: Change order of arguments in macc.sh
| * | | tests: arch: xilinx: Change order of arguments in macc.shJan Kowalewski2019-12-061-1/+1
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* | | Merge pull request #1551 from whitequark/manual-cell-operandsClifford Wolf2019-12-053-43/+82
|\ \ \ | |_|/ |/| | Clarify semantics of comb cells, in particular shifts
| * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-042-8/+26
| | | | | | | | | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
| * | manual: document behavior of many comb cells more precisely.whitequark2019-12-041-35/+56
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* | | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
| | | | | | | | | Fixes #1225.
* | | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-042-146/+196
| | | | | | | | | | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not).
* | | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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* | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-035-114/+571
|\ \ | | | | | | Gowin: add and test DFF init values
| * | update testPepijn de Vos2019-12-031-2/+3
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| * | Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-032-11/+13
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| * | attempt to fix formattingPepijn de Vos2019-11-252-292/+292
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| * | gowin: add and test dff init valuesPepijn de Vos2019-11-254-41/+495
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* | | Merge pull request #1542 from YosysHQ/dave/abc9-loop-fixDavid Shah2019-12-022-29/+46
|\ \ \ | | | | | | | | abc9: Fix breaking of SCCs
| * | | abc9: Fix breaking of SCCsDavid Shah2019-12-012-29/+46
| | |/ | |/| | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-checkClifford Wolf2019-12-011-0/+4
|\ \ \ | |/ / |/| | read_ilang: do bounds checking on bit indices
| * | read_ilang: do bounds checking on bit indicesMarcin Kościelnicki2019-11-271-0/+4
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* | | Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpllMiodrag Milanović2019-11-292-0/+21
|\ \ \ | | | | | | | | xilinx: Add missing blackbox cell for BUFPLL.
| * | | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
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* | | | Revert "Fold loop"Eddie Hung2019-11-271-3/+6
| |/ / |/| | | | | | | | This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35.
* | | Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladdEddie Hung2019-11-272-3/+72
|\ \ \ | | | | | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
| * | | No need for -abc9Eddie Hung2019-11-261-1/+1
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| * | | Add citationEddie Hung2019-11-261-0/+1
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| * | | Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
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| * | | Add testcase derived from fastfir_dynamictaps benchmarkEddie Hung2019-11-261-0/+68
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* | | Merge pull request #1501 from YosysHQ/dave/mem_copy_attrClifford Wolf2019-11-271-0/+4
|\ \ \ | | | | | | | | memory_collect: Copy attr from RTLIL::Memory to cell
| * | | memory_collect: Copy attr from RTLIL::Memory to cellDavid Shah2019-11-181-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fixClifford Wolf2019-11-272-4/+24
|\ \ \ \ | | | | | | | | | | opt_share: Fix handling of fine cells.
| * | | | opt_share: Fix handling of fine cells.Marcin Kościelnicki2019-11-272-4/+24
| | |/ / | |/| | | | | | | | | | Fixes #1525.
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