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* json: Change compat mode to directly emit ints <= 32 bitsR. Ou2020-02-091-3/+3
| | | | | | This increases compatibility with certain older parsers in some cases that worked before commit 15fae357 but do not work with the current compat-int mode
* Remove unnecessary commaEddie Hung2020-02-071-3/+2
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* Merge pull request #1687 from YosysHQ/eddie/fix_ystestsEddie Hung2020-02-072-9/+7
|\ | | | | Fix shiftx2mux, fix yosys-tests
| * techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
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| * Fix misc.abc9.abc9_abc9_lutsEddie Hung2020-02-071-1/+1
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* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-075-27/+42
| | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-076-54/+235
| | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* Merge pull request #1685 from dh73/gowinEddie Hung2020-02-061-1/+1
|\ | | | | Removing cells_sim from GoWin bram techmap
| * Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
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* | Merge pull request #1683 from whitequark/write_verilog-memattrswhitequark2020-02-071-0/+1
|\ \ | | | | | | write_verilog: dump $mem cell attributes
| * | write_verilog: dump $mem cell attributes.whitequark2020-02-061-0/+1
| | | | | | | | | | | | | | | The Verilog backend already dumps attributes on RTLIL::Memory objects but not on `$mem` cells.
* | | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370
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* | | xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-073-1/+39
| | | | | | | | | | | | Part of #1550
* | | Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_mapEddie Hung2020-02-061-109/+43
|\ \ \ | |_|/ |/| | Fix/cleanup +/xilinx/arith_map.v
| * | Fix $lcu -> MUXCY mapping, credit @mwkmwkmwkEddie Hung2020-02-061-4/+5
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| * | Fix/cleanup +/xilinx/arith_map.vEddie Hung2020-02-061-111/+44
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* | | edif: more resilience to mismatched port connection sizes.Marcin Kościelnicki2020-02-061-16/+27
| |/ |/| | | | | Fixes #1653.
* | Merge pull request #1682 from YosysHQ/eddie/opt_after_techmapEddie Hung2020-02-058-5/+9
|\ \ | | | | | | synth_*: call 'opt -fast' after 'techmap'
| * | synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-058-5/+9
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* / shiftx2mux: fix select out of boundsEddie Hung2020-02-053-2/+14
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* Merge pull request #1576 from YosysHQ/eddie/opt_merge_initEddie Hung2020-02-052-1/+65
|\ | | | | opt_merge: discard \init of '$' cells with 'Q' port when merging
| * Merge remote-tracking branch 'origin/master' into eddie/opt_merge_initEddie Hung2020-01-28190-4933/+9266
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| * | Add $_FF_ and $_SR* courtesy of @mwkmwkmwkEddie Hung2019-12-202-23/+33
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| * | More stringent check for flop cellsEddie Hung2019-12-201-2/+4
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| * | opt_merge to discard \init of '$' cells with 'Q' port when mergingEddie Hung2019-12-131-0/+11
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| * | Add testcaseEddie Hung2019-12-131-0/+49
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* | | Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-054-39/+185
|\ \ \ | | | | | | | | techmap LSB-first for compatible $shift/$shiftx cells
| * \ \ Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-0577-1944/+4467
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| * | | | Update tests with reduced areaEddie Hung2020-01-212-6/+6
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| * | | | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
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| * | | | Fix tests -- when Y_WIDTH is non-pow-2Eddie Hung2020-01-211-3/+4
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| * | | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-214-77/+73
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| * | | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-213-0/+149
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* | | | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-052-2/+22
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* | | | Merge pull request #1638 from YosysHQ/eddie/fix1631Eddie Hung2020-02-052-6/+143
|\ \ \ \ | | | | | | | | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
| * | | | More rigorous testEddie Hung2020-01-161-7/+34
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| * | | | clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*Eddie Hung2020-01-152-6/+116
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* | | | | Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-0512-242/+809
|\ \ \ \ \ | | | | | | | | | | | | abc9: add support for required times
| * | | | | abc9_ops: -check for negative arrival/required timesEddie Hung2020-01-271-4/+22
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| * | | | | Fix typoEddie Hung2020-01-271-1/+1
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| * | | | | Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-2726-246/+537
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-153-3/+16
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * | | | | | | Update README.md for (* abc9_required *)Eddie Hung2020-01-151-4/+9
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| * | | | | | | abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-154-4/+4
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-151-1/+2
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| * | | | | | | | abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)Eddie Hung2020-01-142-3/+3
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| * | | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-142-27/+19
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| * | | | | | | | | abc9_ops: -check to check abc9_{arrival,required}Eddie Hung2020-01-141-3/+30
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| * | | | | | | | | abc9_ops: implement a requireds_cacheEddie Hung2020-01-141-26/+34
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| * | | | | | | | | abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-143-78/+106
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