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* xaiger: promote abc9_keep wiresEddie Hung2020-05-251-1/+1
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* tests: add ecp5 latch testcase with -abc9Eddie Hung2020-05-251-0/+16
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* Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidyEddie Hung2020-05-253-13/+15
|\ | | | | xilinx: tidy up cells_sim.v a little
| * tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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| * xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* | Merge pull request #2044 from YosysHQ/eddie/fix2037Eddie Hung2020-05-252-20/+85
|\ \ | |/ |/| verilog: allow attributes on behavioural statements (including null statement)
| * verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
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| * test: add attribute-before-stmt test from @nakengelhardtEddie Hung2020-05-251-0/+15
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| * verilog: do not warn for attributes on null statementsEddie Hung2020-05-252-6/+4
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| * tests: add an generate-else test tooEddie Hung2020-05-251-0/+34
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| * verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
| | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay.
| * verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
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| * tests: add #2037 testcaseEddie Hung2020-05-251-0/+9
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* Merge pull request #2015 from boqwxp/qbfsat-bisectionclairexen2020-05-251-98/+207
|\ | | | | qbfsat: Add an iterative bisection optimization method and make it the default.
| * qbfsat: Remove cruft inadvertently left untouched in commit ↵Alberto Gonzalez2020-05-231-11/+0
| | | | | | | | 86fc49a9d60f9ad4cdeec93663e7245a9fdf60c6.
| * qbfsat: Add bisection mode and make it the default.Alberto Gonzalez2020-05-231-87/+207
| | | | | | | | Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.
* | Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanupEddie Hung2020-05-242-7/+14
|\ \ | | | | | | xaiger: do not derive cells
| * | xaiger: add testcaseEddie Hung2020-05-241-0/+13
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| * | xaiger: do not derive cellsEddie Hung2020-05-241-7/+1
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* | | Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanupEddie Hung2020-05-233-14/+0
|\ \ \ | |/ / |/| | ecp5: cleanup unused +/ecp5/abc9_model.v
| * | ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-233-14/+0
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* | Merge pull request #2072 from whitequark/cxxrtl-dont-purgewhitequark2020-05-221-8/+2
|\ \ | | | | | | cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level
| * | cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.whitequark2020-05-221-8/+2
| | | | | | | | | | | | | | | | | | This isn't actually necessary anymore after scheduling was improved, and `clean -purge` disrupts the mapping between wires in the input RTLIL netlist and the output CXXRTL code.
* | | abc9_ops: update commentEddie Hung2020-05-211-1/+1
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* | | Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-212-11/+37
|\ \ \ | | | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| * | | Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| | | | | | | | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| * | | verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
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| * | | tests: attributes before task enableEddie Hung2020-05-141-0/+28
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* | | | Merge pull request #2059 from boqwxp/logger-vector-to-dictMiodrag Milanović2020-05-213-51/+21
|\ \ \ \ | |_|/ / |/| | | log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
| * | | log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, ↵Alberto Gonzalez2020-05-153-51/+21
| | | | | | | | | | | | | | | | warning, log}` to better express the intent that each element is unique.
* | | | Merge pull request #2046 from PeterCrozier/trapN. Engelhardt2020-05-201-3/+3
|\ \ \ \ | | | | | | | | | | Extend YS_DEBUGTRAP to MacOS.
| * | | | Consolidate Linux and Mac version of YS_DEBUGTRAP_IF_DEBUGGING.Peter Crozier2020-05-131-5/+2
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| * | | | Extend YS_DEBUGTRAP to MacOS.Peter Crozier2020-05-131-1/+4
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* | | | Merge pull request #2054 from boqwxp/fix-smtbmcN. Engelhardt2020-05-201-3/+3
|\ \ \ \ | | | | | | | | | | smtbmc: Fix return status handling.
| * | | | smtbmc: Fix typo in error message.Alberto Gonzalez2020-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
| * | | | smtbmc: Fix return status handling.Alberto Gonzalez2020-05-141-2/+2
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* | | | | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-1943-27/+258
| | | | | | | | | | | | | | | | | | | | Fixes #2058.
* | | | | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dffEddie Hung2020-05-1834-1853/+1656
|\ \ \ \ \ | | | | | | | | | | | | abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
| * | | | | abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-145-23/+11
| | | | | | | | | | | | | | | | | | | | | | | | instead of moving them to $__ prefix
| * | | | | abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)Eddie Hung2020-05-141-4/+6
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| * | | | | abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-144-25/+13
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| * | | | | Fix broken test when ignoring abc9_flop with init == 1'b1Eddie Hung2020-05-141-3/+0
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| * | | | | abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-144-135/+121
| | | | | | | | | | | | | | | | | | | | | | | | replacing _all_ (* abc9_box *) instantiations with their derived types
| * | | | | Cleanup; reduce Module::derive() callsEddie Hung2020-05-144-153/+164
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| * | | | | ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
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| * | | | | ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
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| * | | | | ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
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| * | | | | abc9: update to =_$abc9_flops pattern which includes whiteboxesEddie Hung2020-05-141-3/+3
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| * | | | | abc9_ops: update docsEddie Hung2020-05-141-11/+10
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| * | | | | xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
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