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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 16:39:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 16:39:16 -0700 |
| commit | 1dce798dc5050745490600c09c873d821548f4f7 (patch) | |
| tree | c993ce9fc1d225b7c758510a15563af4e655159f | |
| parent | a7f2ef6d34c4b336a910b3c6f3d2cc11da8a82b4 (diff) | |
| download | yosys-1dce798dc5050745490600c09c873d821548f4f7.tar.gz yosys-1dce798dc5050745490600c09c873d821548f4f7.tar.bz2 yosys-1dce798dc5050745490600c09c873d821548f4f7.zip | |
tests: add ecp5 latch testcase with -abc9
| -rw-r--r-- | tests/arch/ecp5/latches_abc9.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys new file mode 100644 index 000000000..ca3182254 --- /dev/null +++ b/tests/arch/ecp5/latches_abc9.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module top(input e, d, output q); +reg l; +always @* + if (e) + l = ~d; +assign q = ~l; +endmodule +EOT +proc +design -save gold + +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ecp5 -abc9 +select -assert-count 2 t:LUT4 +select -assert-none t:LUT4 %% t:* %D |