| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | ecp5: Demote conflicting FF init values to a warning | David Shah | 2019-03-04 | 1 | -2/+7 | |
| * | | | | Add missing newline | Clifford Wolf | 2019-03-05 | 1 | -1/+1 | |
| * | | | | Merge pull request #851 from kprasadvnsi/master | Clifford Wolf | 2019-03-05 | 7 | -0/+55 | |
| |\ \ \ \ | ||||||
| | * | | | | Added examples/anlogic/ | Kali Prasad | 2019-03-04 | 7 | -0/+55 | |
| * | | | | | Merge pull request #852 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-03-05 | 2 | -2/+2 | |
| |\ \ \ \ \ | ||||||
| | * | | | | | Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails | Jim Lawson | 2019-03-04 | 2 | -2/+2 | |
| | |/ / / / | ||||||
| * / / / / | Use "write_edif -pvector bra" for Xilinx EDIF files | Clifford Wolf | 2019-03-05 | 1 | -1/+1 | |
| |/ / / / | ||||||
| * | | | | Improve igloo2 example | Clifford Wolf | 2019-03-03 | 2 | -3/+10 | |
| * | | | | Update igloo2 example to Libero v12.0 | Clifford Wolf | 2019-03-03 | 2 | -6/+5 | |
| * | | | | Merge pull request #848 from YosysHQ/clifford/fix763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 | |
| |\ \ \ \ | ||||||
| | * | | | | Fix error for wire decl in always block, fixes #763 | Clifford Wolf | 2019-03-02 | 1 | -1/+5 | |
| * | | | | | Merge pull request #849 from YosysHQ/clifford/dynports | Clifford Wolf | 2019-03-02 | 4 | -1/+24 | |
| |\ \ \ \ \ | |/ / / / |/| | | | | ||||||
| | * | | | | Only run derive on blackbox modules when ports have dynamic size | Clifford Wolf | 2019-03-02 | 4 | -1/+24 | |
| |/ / / / | ||||||
| * | | | | Fix $global_clock handling vs autowire | Clifford Wolf | 2019-03-02 | 1 | -1/+1 | |
| * | | | | Merge pull request #847 from YosysHQ/clifford/fix785 | Clifford Wolf | 2019-03-02 | 1 | -0/+35 | |
| |\ \ \ \ | ||||||
| | * | | | | Fix $readmem[hb] for mem2reg memories, fixes #785 | Clifford Wolf | 2019-03-02 | 1 | -0/+35 | |
| |/ / / / | ||||||
| * | | | | Merge pull request #843 from YosysHQ/clifford/mem2regconstidx | Clifford Wolf | 2019-03-02 | 2 | -0/+13 | |
| |\ \ \ \ | ||||||
| | * | | | | Use mem2reg on memories that only have constant-index write ports | Clifford Wolf | 2019-03-01 | 2 | -0/+13 | |
| * | | | | | Merge pull request #845 from YosysHQ/clifford/travisnomacos | Clifford Wolf | 2019-03-02 | 1 | -5/+5 | |
| |\ \ \ \ \ | |_|/ / / |/| | | | | ||||||
| | * | | | | Disable macOS builds in Travis | Clifford Wolf | 2019-03-02 | 1 | -5/+5 | |
| |/ / / / | ||||||
| * | | | | Try again for passes/pmgen/ice40_dsp_pm.h rule | Larry Doolittle | 2019-03-01 | 2 | -8/+9 | |
| * | | | | Minor improvements in README | Clifford Wolf | 2019-03-01 | 1 | -3/+16 | |
| |/ / / | ||||||
| * / / | Fix "write_edif -gndvccy" | Clifford Wolf | 2019-03-01 | 1 | -1/+1 | |
| |/ / | ||||||
| * | | Merge pull request #841 from mmicko/master | Clifford Wolf | 2019-03-01 | 1 | -2/+3 | |
| |\ \ | ||||||
| | * | | Fix ECP5 cells_sim for iverilog | Miodrag Milanovic | 2019-03-01 | 1 | -2/+3 | |
| |/ / | ||||||
| * | | Improve "read" error msg | Clifford Wolf | 2019-02-28 | 1 | -1/+1 | |
| * | | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode | Clifford Wolf | 2019-02-28 | 1 | -2/+2 | |
| |\ \ | ||||||
| | * | | ice40: use 2 bits for READ/WRITE MODE for SB_RAM map | Elms | 2019-02-28 | 1 | -2/+2 | |
| * | | | Hotfix for "make test" | Clifford Wolf | 2019-02-28 | 1 | -1/+1 | |
| * | | | Merge pull request #837 from YosysHQ/clifford/fix835 | Clifford Wolf | 2019-02-28 | 1 | -5/+24 | |
| |\ \ \ | ||||||
| | * | | | Fix multiple issues in wreduce FF handling, fixes #835 | Clifford Wolf | 2019-02-28 | 1 | -5/+24 | |
| |/ / / | ||||||
| * | | | Merge pull request #834 from YosysHQ/clifford/siminit | Clifford Wolf | 2019-02-28 | 2 | -3/+12 | |
| |\ \ \ | ||||||
| | * | | | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 2 | -3/+12 | |
| |/ / / | ||||||
| * | | | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 9 | -29/+29 | |
| * | | | Fix pmgen for in-tree builds | Clifford Wolf | 2019-02-28 | 2 | -8/+9 | |
| * | | | Merge pull request #794 from daveshah1/ecp5improve | Clifford Wolf | 2019-02-28 | 7 | -12/+388 | |
| |\ \ \ | ||||||
| | * | | | ecp5: Compatibility with Migen AsyncResetSynchronizer | David Shah | 2019-02-25 | 2 | -0/+20 | |
| | * | | | ecp5: Add DDRDLLA | David Shah | 2019-02-19 | 1 | -0/+9 | |
| | * | | | ecp5: Add DELAYF/DELAYG blackboxes | David Shah | 2019-02-19 | 1 | -0/+18 | |
| | * | | | ecp5: Add ECLKSYNCB blackbox | David Shah | 2019-02-13 | 1 | -1/+7 | |
| | * | | | ecp5: Full set of IO-related blackboxes | David Shah | 2019-02-12 | 1 | -0/+102 | |
| | * | | | ecp5: Support for flipflop initialisation | David Shah | 2019-01-22 | 3 | -4/+199 | |
| | * | | | ecp5: Add LSRMODE to flipflops for PRLD support | David Shah | 2019-01-21 | 1 | -7/+16 | |
| | * | | | ecp5: More blackboxes | David Shah | 2019-01-21 | 1 | -0/+17 | |
| | * | | | ecp5: Increase threshold for ALU mapping | David Shah | 2019-01-21 | 1 | -1/+1 | |
| * | | | | Merge pull request #827 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-28 | 4 | -11/+21 | |
| |\ \ \ \ | |_|/ / |/| | | | ||||||
| | * | | | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 4 | -11/+21 | |
| * | | | | Fix pmgen for out-of-tree build | Clifford Wolf | 2019-02-28 | 2 | -4/+6 | |
| * | | | | Merge pull request #833 from YosysHQ/clifford/fix831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 | |
| |\ \ \ \ | ||||||
| | * | | | | Fix smt2 code generation for partially initialized memowy words, fixes #831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 | |
| |/ / / / | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |