iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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\| \| * \| \| \|	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-04-30	91	-445/+5146
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\| \| * \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-04-09	8	-7/+76
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\| \| * \ \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-04-03	3	-30/+203
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\| \| * \ \ \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-04-01	120	-600/+5502
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\| \| * \ \ \ \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-03-04	12	-28/+124
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\| \| * \ \ \ \ \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-03-01	31	-105/+622
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\| \| * \ \ \ \ \ \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-02-25	39	-222/+2479
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\| \| * \ \ \ \ \ \ \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-02-15	3	-44/+47
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\| \| * \ \ \ \ \ \ \ \ \ \ \	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2019-02-11	109	-413/+3479
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\| \| * \| \| \| \| \| \| \| \| \| \| \| \|	Fix botched merge in CHANGELOG	Jim Lawson	2018-12-18	1	-1/+0
\| \| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2018-12-18	128	-636/+8336
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\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Improve Verific importer blackbox handling	Clifford Wolf	2018-10-08	1	-2/+14
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Add "write_edif -attrprop"	Clifford Wolf	2018-10-08	1	-11/+28
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix compiler warning in verific.cc	Clifford Wolf	2018-10-08	1	-0/+2
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix misspelling in issue_template.md	Tim Ansell	2018-10-08	1	-1/+1
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix IdString M in setup_stdcells()	Adrian Wheeldon	2018-10-08	1	-1/+1
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Add inout ports to cells_xtra.v	Clifford Wolf	2018-10-08	2	-2/+14
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	xilinx: Adding missing inout IO port to IOBUF	Tim Ansell	2018-10-08	1	-0/+1
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix for issue 594.	Tom Verbeure	2018-10-08	1	-1/+2
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Add read_verilog $changed support	Dan Gisselquist	2018-10-08	1	-1/+4
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	ecp5: Don't map ROMs to DRAM	David Shah	2018-10-08	1	-0/+1
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix handling of $past 2nd argument in read_verilog	Clifford Wolf	2018-10-08	1	-1/+1
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Update to v2 YosysVS template	Clifford Wolf	2018-10-08	1	-4/+4
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Add "read_verilog -noassert -noassume -assert-assumes"	Clifford Wolf	2018-10-08	3	-6/+49
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Added support for ommited "parameter" in Verilog-2001 style parameter decl in...	Clifford Wolf	2018-10-08	1	-3/+9
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Update CHANGELOG	Clifford Wolf	2018-10-08	1	-2/+35
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	added prefix to FDirection constants, fixing windows build	Miodrag Milanovic	2018-10-08	1	-11/+11
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Update CHANGLELOG	Clifford Wolf	2018-10-08	1	-5/+27
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Update Changelog	Clifford Wolf	2018-10-08	1	-1/+54
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix Cygwin build and document needed packages	Miodrag Milanovic	2018-10-08	3	-1/+14
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Fixed typo in "verilog_write" help message	acw1251	2018-10-08	2	-5/+5
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'upstream/master'	Jim Lawson	2018-09-17	11	-14/+78
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\| \| * \ \ \ \ \ \ \ \ \ \ \ \ \ \	Merge pull request #4 from YosysHQ/master	Jim Lawson	2018-08-28	3	-23/+112
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\| * \| \ \ \ \ \ \ \ \ \ \ \ \ \ \ \	Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_braces	Eddie Hung	2019-05-21	1	-5/+9
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\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Rename label	Eddie Hung	2019-05-21	1	-6/+5
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Try again	Eddie Hung	2019-05-21	1	-4/+10
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix warning	Eddie Hung	2019-05-21	1	-3/+2
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* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Add whitebox support to DRAM	Eddie Hung	2019-05-23	5	-24/+26
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	shift register inference before mux	Eddie Hung	2019-05-22	1	-3/+3
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix/workaround symptom unveiled by #1023	Eddie Hung	2019-05-21	1	-4/+14
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Instead of MUXCY/XORCY use CARRY4 (with timing)	Eddie Hung	2019-05-21	4	-11/+20
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Pad all boxes so that all input/output connections specified	Eddie Hung	2019-05-21	1	-22/+67
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Modify LUT area cost to be same as old abc	Eddie Hung	2019-05-21	1	-10/+9
* \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-05-21	56	-485/+1809
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1017 from Kmanfi/bigger_verilog_files	Clifford Wolf	2019-05-18	1	-1/+1
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\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Read bigger Verilog files.	Kaj Tuomi	2019-05-18	1	-1/+1
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\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1013 from antmicro/parameter_attributes	Clifford Wolf	2019-05-16	3	-2/+24
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\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Added tests for Verilog frontent for attributes on parameters and localparams	Maciej Kurc	2019-05-16	2	-0/+22
\| \| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Added support for parsing attributes on parameters in Verilog frontent. Conte...	Maciej Kurc	2019-05-16	1	-2/+2
\| * \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #1012 from YosysHQ/clifford/sigspecrw	Clifford Wolf	2019-05-15	3	-17/+92
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