Merge pull request #1013 from antmicro/parameter_attributes

Support for attributes on parameters and localparams for Verilog frontend

3 files changed, 24 insertions, 2 deletions

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e82c2781c..132468f0c 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1202,7 +1202,7 @@ param_range:
 	};
 
 param_decl:
-	TOK_PARAMETER {
+	attr TOK_PARAMETER {
 		astbuf1 = new AstNode(AST_PARAMETER);
 		astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 	} param_signed param_integer param_real param_range param_decl_list ';' {
@@ -1210,7 +1210,7 @@ param_decl:
 	};
 
 localparam_decl:
-	TOK_LOCALPARAM {
+	attr TOK_LOCALPARAM {
 		astbuf1 = new AstNode(AST_LOCALPARAM);
 		astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 	} param_signed param_integer param_real param_range param_decl_list ';' {
diff --git a/tests/simple/localparam_attr.v b/tests/simple/localparam_attr.v
new file mode 100644
index 000000000..2ef76c71c
--- /dev/null
+++ b/tests/simple/localparam_attr.v
@@ -0,0 +1,11 @@
+module uut_localparam_attr (I, O);
+
+(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)
+localparam WIDTH = 1;
+
+input  wire [WIDTH-1:0] I;
+output wire [WIDTH-1:0] O;
+
+assign O = I;
+
+endmodule
diff --git a/tests/simple/param_attr.v b/tests/simple/param_attr.v
new file mode 100644
index 000000000..34d63a34e
--- /dev/null
+++ b/tests/simple/param_attr.v
@@ -0,0 +1,11 @@
+module uut_param_attr (I, O);
+
+(* PARAMETER_ATTRIBUTE = "attribute_content" *)
+parameter WIDTH = 1;
+
+input  wire [WIDTH-1:0] I;
+output wire [WIDTH-1:0] O;
+
+assign O = I;
+
+endmodule