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* Bump versiongithub-actions[bot]2021-10-161-1/+1
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* Merge pull request #3044 from YosysHQ/micko/verific_bufif1Claire Xen2021-10-151-2/+2
|\ | | | | Support PRIM_BUFIF1 primitive, fixes #2981
| * Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
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* Bump versiongithub-actions[bot]2021-10-121-1/+1
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* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
|\ | | | | Add support for $aldff flip-flops to verific importer
| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Merge pull request #3040 from YosysHQ/micko/split_module_portsClaire Xen2021-10-111-0/+2
|\ \ | | | | | | Split module ports, 20 per line
| * | Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
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* | | Merge pull request #3041 from YosysHQ/mmicko/module_attrClaire Xen2021-10-111-0/+1
|\ \ \ | |/ / |/| | Import module attributes from Verific
| * | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* | Bump versiongithub-actions[bot]2021-10-091-1/+1
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* | Fix a regression from #3035.Marcelina Kościelnicka2021-10-082-1/+22
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* Bump versiongithub-actions[bot]2021-10-081-1/+1
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-0714-546/+660
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* Bump versiongithub-actions[bot]2021-10-051-1/+1
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* verific set db_infer_set_reset_registersMiodrag Milanovic2021-10-041-0/+1
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* Bump versiongithub-actions[bot]2021-10-031-1/+1
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* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-029-11/+77
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* zinit: Refactor to use FfData.Marcelina Kościelnicka2021-10-021-101/+38
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* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-0210-325/+565
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-029-2/+527
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* Specify minimum bison version 3.0+Zachary Snow2021-10-012-0/+4
| | | | | | | | | Yosys works with bison 3.0 (or newer), but not bison 2.7 (the previous release). Ideally, we would require "3" rather than "3.0" to give a better error message, but bison 2.3, which still ships with macOS, does not support major-only version requirements. With this change, building with an outdated bison yields: `frontends/rtlil/rtlil_parser.y:25.10-14: require bison 3.0, but have 2.3`.
* simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-023-290/+26
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* Merge pull request #3017 from YosysHQ/claire/short_rtlil_x_constMiodrag Milanović2021-09-281-9/+13
|\ | | | | Add optimization to rtlil back-end for all-x parameter values
| * Add optimization to rtlil back-end for all-x parameter valuesClaire Xenia Wolf2021-09-271-9/+13
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Bump versiongithub-actions[bot]2021-09-281-1/+1
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* | Prepare for next release cycleMiodrag Milanovic2021-09-272-3/+6
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* Bump versiongithub-actions[bot]2021-09-251-1/+1
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* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-2441-79/+80
|\ | | | | Fix "make vgtest"
| * Fix TOK_ID memory leak in for_initializationZachary Snow2021-09-231-0/+1
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| * Fix "make vgtest" so it runs to the end (but now it fails ;)Claire Xenia Wolf2021-09-2340-79/+79
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Bump versiongithub-actions[bot]2021-09-221-1/+1
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* | sv: support wand and wor of data typesZachary Snow2021-09-214-10/+53
| | | | | | | | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-214-4/+110
|/ | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* Bump versiongithub-actions[bot]2021-09-191-1/+1
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* Merge pull request #3010 from the6p4c/masterMiodrag Milanović2021-09-181-0/+2
|\ | | | | Fix protobuf backend build dependencies - intermittent build issue due to missing rule
| * Fix protobuf backend build dependenciesthe6p4c2021-09-171-0/+2
|/ | | | | | | backends/protobuf/protobuf.cc depends on the source and header files generated by protoc, but this dependency wasn't explicitly declared. Add a rule to the Makefile to fix intermittent build failures when the protobuf header/source file isn't built before protobuf.cc.
* Bump versiongithub-actions[bot]2021-09-141-1/+1
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* verilog: Squash flex-triggered warning.Marcelina Kościelnicka2021-09-131-0/+2
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* Updates for CHANGELOG (#2997)Miodrag Milanović2021-09-131-48/+126
| | | Added missing changes from git log and group items
* Bump versiongithub-actions[bot]2021-09-111-1/+1
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* Merge pull request #3001 from YosysHQ/claire/sigcheckMiodrag Milanović2021-09-102-6/+14
|\ | | | | Add additional check to SigSpec
| * Add additional check to SigSpecClaire Xenia Wolf2021-09-102-6/+14
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* yosys-smtbmc: Fix reused loop variable.Marcelina Kościelnicka2021-09-101-4/+4
| | | | Fixes #2999.
* Bump versiongithub-actions[bot]2021-09-101-1/+1
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* abc9: make re-entrant (#2993)Eddie Hung2021-09-093-9/+29
| | | | | | | | | * Add testcase * Cleanup some state at end of abc9 * Re-assign abc9_box_id from scratch * Suppress delete unless prep_bypass did something
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-092-1/+15
| | | | | * Add testcase * holes module to instantiate cells with NEW_ID
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-093-7/+30
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
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