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xilinx/ice40/ecp5: zinit requires selected wires, so select them all
Eddie Hung
2020-05-14
3
-4
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+4
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abc9_ops: move assert
Eddie Hung
2020-05-14
1
-1
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+1
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abc9: put 'aigmap' back
Eddie Hung
2020-05-14
1
-0
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+1
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xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
Eddie Hung
2020-05-14
3
-4
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+198
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abc9_ops: fix bypass boxes using (* abc9_bypass *)
Eddie Hung
2020-05-14
2
-14
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+10
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abc9_ops: tidy up, suppress error if no boxes/holes
Eddie Hung
2020-05-14
1
-18
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+18
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abc9_ops: -prep_delays to not insert delay box if input connection is const
Eddie Hung
2020-05-14
1
-0
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+2
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abc9_ops: cleanup; -prep_dff -> -prep_dff_submod
Eddie Hung
2020-05-14
2
-22
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+14
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abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eddie Hung
2020-05-14
11
-941
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+667
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abc9_ops: -reintegrate to handle $_FF_; cleanup
Eddie Hung
2020-05-14
1
-22
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+18
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xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity
Eddie Hung
2020-05-14
1
-16
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+5
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aiger: -xaiger to return $_FF_ flops
Eddie Hung
2020-05-14
1
-15
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+2
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abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
Eddie Hung
2020-05-14
4
-12
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+48
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abc9: test to use box file instead of auto
Eddie Hung
2020-05-14
3
-2
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+5
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abc9: restore selected_modules()
Eddie Hung
2020-05-14
1
-1
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+1
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synth_*: no need to explicitly read +/abc9_model.v
Eddie Hung
2020-05-14
4
-4
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+3
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Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"
Eddie Hung
2020-05-14
1
-4
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+0
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abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
Eddie Hung
2020-05-14
7
-24
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+88
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kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
Eddie Hung
2020-05-14
1
-10
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+6
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abc9_ops: -prep_dff_map to error if async flop found
Eddie Hung
2020-05-14
2
-9
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+7
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Uncomment negative setup times; clamp to zero for connectivity
Eddie Hung
2020-05-14
1
-13
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+29
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abc9: remove redundant wbflip
Eddie Hung
2020-05-14
1
-1
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+0
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xaiger: always sort input/output bits by port id
Eddie Hung
2020-05-14
1
-12
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+10
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abc9: generate $abc9_holes design instead of <name>$holes
Eddie Hung
2020-05-14
3
-18
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+28
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abc9_ops: more robust
Eddie Hung
2020-05-14
1
-8
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+14
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abc9: suppress warnings when no compatible + used flop boxes formed
Eddie Hung
2020-05-14
3
-38
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+66
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xilinx: update abc9_dff tests
Eddie Hung
2020-05-14
1
-18
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+45
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xilinx: remove no-longer-relevant test
Eddie Hung
2020-05-14
1
-91
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+0
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aiger/xaiger: use odd for negedge clk, even for posedge
Eddie Hung
2020-05-14
2
-10
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+13
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abc9: cleanup
Eddie Hung
2020-05-14
1
-7
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+11
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Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"
Eddie Hung
2020-05-14
3
-220
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+64
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abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output
Eddie Hung
2020-05-14
1
-1
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+5
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abc9_ops: do away with '$abc9_cells' selection
Eddie Hung
2020-05-14
2
-40
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+30
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abc9_ops: use new 'design -delete' and 'select -unset'
Eddie Hung
2020-05-14
2
-16
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+7
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ecp5: (* abc9_flop *) gated behind YOSYS
Eddie Hung
2020-05-14
1
-0
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+2
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submod: revert accidental change
Eddie Hung
2020-05-14
1
-1
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+1
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Revert "Merge branch 'eddie/kernel_makeblackbox' into eddie/abc9_auto_dff"
Eddie Hung
2020-05-14
1
-1
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+0
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xaiger: update help text
Eddie Hung
2020-05-14
1
-4
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+4
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ecp5: add synth_ecp5 -dff to work with -abc9
Eddie Hung
2020-05-14
2
-12
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+47
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abc9_ops: -prep_dff_map to warn if no specify cells
Eddie Hung
2020-05-14
1
-7
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+12
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ice40: synth_ice40 cleanup
Eddie Hung
2020-05-14
1
-13
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+3
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ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init
Eddie Hung
2020-05-14
3
-64
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+220
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kernel: Module::makeblackbox() to clear connections + delete wires last
Eddie Hung
2020-05-14
1
-0
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+1
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ice40: add synth_ice40 -dff option, support with -abc9
Eddie Hung
2020-05-14
2
-8
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+41
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ice40: split out cells_map.v into ff_map.v
Eddie Hung
2020-05-14
3
-31
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+29
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abc9_ops: -prep_dff_map to cope with plain $_DFF_[NP]_ flops
Eddie Hung
2020-05-14
1
-12
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+39
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synth_xilinx: rename dff_mode -> dff
Eddie Hung
2020-05-14
1
-8
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+10
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xaiger: do not treat (* init=1'bx *) as 1'b0
Eddie Hung
2020-05-14
1
-1
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+1
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abc9: cleanup
Eddie Hung
2020-05-14
1
-4
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+1
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abc9_ops: do not use (* abc9_init *)
Eddie Hung
2020-05-14
1
-16
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+31
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