| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 16 | -37/+37 |
| * | More bugfixes related to new RTLIL::IdString | Clifford Wolf | 2014-08-02 | 10 | -44/+60 |
| * | Limit size of log_signal buffer to 100 elements | Clifford Wolf | 2014-08-02 | 2 | -2/+9 |
| * | Improvements in new RTLIL::IdString implementation | Clifford Wolf | 2014-08-02 | 5 | -33/+65 |
| * | Fixed a performance bug in opt_reduce | Clifford Wolf | 2014-08-02 | 1 | -2/+6 |
| * | Implemented new reference counting RTLIL::IdString | Clifford Wolf | 2014-08-02 | 2 | -15/+90 |
| * | Fixed memory corruption related to id2cstr() | Clifford Wolf | 2014-08-02 | 1 | -2/+2 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 33 | -261/+237 |
| * | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 | 12 | -32/+71 |
| * | Added logfile hash to statistics footer | Clifford Wolf | 2014-08-01 | 5 | -45/+79 |
| * | Replaced sha1 implementation | Clifford Wolf | 2014-08-01 | 8 | -283/+334 |
| * | Added per-pass cpu usage statistics | Clifford Wolf | 2014-08-01 | 4 | -12/+86 |
| * | Added ModIndex helper class, some changes to RTLIL::Monitor | Clifford Wolf | 2014-08-01 | 9 | -30/+170 |
| * | Packed SigBit::data and SigBit::offset in a union | Clifford Wolf | 2014-08-01 | 2 | -10/+14 |
| * | Consolidated hana test benches into fewer files | Clifford Wolf | 2014-08-01 | 175 | -1332/+1622 |
| * | Added "test_autotb -n <num_iter>" option | Clifford Wolf | 2014-08-01 | 2 | -11/+32 |
| * | Renamed modwalker.h to modtools.h | Clifford Wolf | 2014-07-31 | 3 | -12/+14 |
| * | Various cleanups in Makefile, Renamed default configurations | Clifford Wolf | 2014-07-31 | 1 | -21/+12 |
| * | Added compiler + compiler version + compiler flags to version string | Clifford Wolf | 2014-07-31 | 1 | -1/+2 |
| * | Fixed build of verific bindings | Clifford Wolf | 2014-07-31 | 1 | -11/+11 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 46 | -1059/+1086 |
| * | Added "trace" command | Clifford Wolf | 2014-07-31 | 4 | -2/+103 |
| * | Added RTLIL::Monitor | Clifford Wolf | 2014-07-31 | 2 | -96/+97 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 15 | -44/+142 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 41 | -665/+790 |
| * | Renamed "stdcells.v" to "techmap.v" | Clifford Wolf | 2014-07-31 | 9 | -12/+15 |
| * | Added "techmap -assert" | Clifford Wolf | 2014-07-31 | 2 | -14/+43 |
| * | Reorganized stdcells.v (no actual code change, just moved and indented stuff) | Clifford Wolf | 2014-07-31 | 1 | -747/+590 |
| * | Added "yosys -A" | Clifford Wolf | 2014-07-31 | 1 | -1/+10 |
| * | Added "yosys -Q" | Clifford Wolf | 2014-07-31 | 1 | -26/+35 |
| * | Added techmap CONSTMAP feature | Clifford Wolf | 2014-07-30 | 3 | -12/+126 |
| * | Fixed counting verilog line numbers for "// synopsys translate_off" sections | Clifford Wolf | 2014-07-30 | 2 | -4/+4 |
| * | Added write_file command | Clifford Wolf | 2014-07-30 | 4 | -5/+84 |
| * | Added "make -j{N}" support to "make test" | Clifford Wolf | 2014-07-30 | 7 | -22/+39 |
| * | Improvements in test_cell | Clifford Wolf | 2014-07-30 | 1 | -35/+89 |
| * | New techmap default rules for $shr $sshr $shl $sshl | Clifford Wolf | 2014-07-30 | 1 | -282/+62 |
| * | Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models | Clifford Wolf | 2014-07-30 | 1 | -36/+39 |
| * | Added native support for shift operations to ezSAT | Clifford Wolf | 2014-07-30 | 2 | -1/+95 |
| * | Added "log_dump_val_worker(char *v)" | Clifford Wolf | 2014-07-30 | 1 | -0/+1 |
| * | Added CodingStyle document | Clifford Wolf | 2014-07-30 | 1 | -0/+43 |
| * | Added "kernel/yosys.h" and "kernel/yosys.cc" | Clifford Wolf | 2014-07-30 | 8 | -61/+133 |
| * | Added "test_cell" command | Clifford Wolf | 2014-07-29 | 3 | -1/+186 |
| * | Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ | Clifford Wolf | 2014-07-29 | 5 | -10/+12 |
| * | Fixed Verilog pre-processor for files with no trailing newline | Clifford Wolf | 2014-07-29 | 1 | -1/+1 |
| * | Bugfix in simlib.v for iverilog | Clifford Wolf | 2014-07-29 | 1 | -5/+6 |
| * | Allow "hierarchy -generate" for $__ cells | Clifford Wolf | 2014-07-29 | 1 | -1/+3 |
| * | Added "techmap -map %{design-name}" | Clifford Wolf | 2014-07-29 | 4 | -10/+29 |
| * | Added $shift and $shiftx cell types (needed for correct part select behavior) | Clifford Wolf | 2014-07-29 | 12 | -40/+214 |
| * | Removed left over debug code | Clifford Wolf | 2014-07-28 | 2 | -2/+0 |
| * | Fixed part selects of parameters | Clifford Wolf | 2014-07-28 | 2 | -7/+31 |
