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author | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:06:27 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-29 16:35:13 +0200 |
commit | 03c96f9ce7120adf1c9bab93485a3b4bf6493ae9 (patch) | |
tree | c59b7586ba36ebc0dc1576337c882b44db5f8dc5 | |
parent | 397b00252dc0c4af725614bd12fc299147ba8efa (diff) | |
download | yosys-03c96f9ce7120adf1c9bab93485a3b4bf6493ae9.tar.gz yosys-03c96f9ce7120adf1c9bab93485a3b4bf6493ae9.tar.bz2 yosys-03c96f9ce7120adf1c9bab93485a3b4bf6493ae9.zip |
Added "techmap -map %{design-name}"
-rw-r--r-- | kernel/rtlil.cc | 5 | ||||
-rw-r--r-- | kernel/rtlil.h | 5 | ||||
-rw-r--r-- | passes/techmap/extract.cc | 6 | ||||
-rw-r--r-- | passes/techmap/techmap.cc | 23 |
4 files changed, 29 insertions, 10 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 83bbd7b17..f864d88c0 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -219,6 +219,11 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) } } +RTLIL::Design::Design() +{ + refcount_modules_ = 0; +} + RTLIL::Design::~Design() { for (auto it = modules_.begin(); it != modules_.end(); it++) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e8d05e7e4..1f25542f3 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -352,11 +352,16 @@ struct RTLIL::Design std::map<RTLIL::IdString, RTLIL::Selection> selection_vars; std::string selected_active_module; + Design(); ~Design(); RTLIL::ObjRange<RTLIL::Module*> modules(); RTLIL::Module *module(RTLIL::IdString name); + bool has(RTLIL::IdString id) const { + return modules_.count(id) != 0; + } + void add(RTLIL::Module *module); RTLIL::Module *addModule(RTLIL::IdString name); void remove(RTLIL::Module *module); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 9c5fa7f71..19d323341 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -603,9 +603,9 @@ struct ExtractPass : public Pass { delete map; log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1); } - for (auto &it : saved_designs.at(filename.substr(1))->modules_) - if (!map->modules_.count(it.first)) - map->modules_[it.first] = it.second->clone(); + for (auto mod : saved_designs.at(filename.substr(1))->modules()) + if (!map->has(mod->name)) + map->add(mod->clone()); } else { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 5a69baca5..0ae5220e0 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -656,13 +656,22 @@ struct TechmapPass : public Pass { Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend); fclose(f); } else - for (auto &fn : map_files) { - FILE *f = fopen(fn.c_str(), "rt"); - if (f == NULL) - log_cmd_error("Can't open map file `%s'\n", fn.c_str()); - Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend); - fclose(f); - } + for (auto &fn : map_files) + if (fn.substr(0, 1) == "%") { + if (!saved_designs.count(fn.substr(1))) { + delete map; + log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1); + } + for (auto mod : saved_designs.at(fn.substr(1))->modules()) + if (!map->has(mod->name)) + map->add(mod->clone()); + } else { + FILE *f = fopen(fn.c_str(), "rt"); + if (f == NULL) + log_cmd_error("Can't open map file `%s'\n", fn.c_str()); + Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend); + fclose(f); + } std::map<RTLIL::IdString, RTLIL::Module*> modules_new; for (auto &it : map->modules_) { |