Renamed port access function on RTLIL::Cell, added param access functions

46 files changed, 1086 insertions, 1059 deletions

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index d167c3f4e..b31d6ce6f 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -145,56 +145,56 @@ struct BlifDumper
 
 			if (!config->icells_mode && cell->type == "$_INV_") {
 				fprintf(f, ".names %s %s\n0 1\n",
-						cstr(cell->get("\\A")), cstr(cell->get("\\Y")));
+						cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_AND_") {
 				fprintf(f, ".names %s %s %s\n11 1\n",
-						cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
+						cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_OR_") {
 				fprintf(f, ".names %s %s %s\n1- 1\n-1 1\n",
-						cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
+						cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_XOR_") {
 				fprintf(f, ".names %s %s %s\n10 1\n01 1\n",
-						cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
+						cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_MUX_") {
 				fprintf(f, ".names %s %s %s %s\n1-0 1\n-11 1\n",
-						cstr(cell->get("\\A")), cstr(cell->get("\\B")),
-						cstr(cell->get("\\S")), cstr(cell->get("\\Y")));
+						cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
+						cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_DFF_N_") {
 				fprintf(f, ".latch %s %s fe %s\n",
-						cstr(cell->get("\\D")), cstr(cell->get("\\Q")), cstr(cell->get("\\C")));
+						cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\C")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$_DFF_P_") {
 				fprintf(f, ".latch %s %s re %s\n",
-						cstr(cell->get("\\D")), cstr(cell->get("\\Q")), cstr(cell->get("\\C")));
+						cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\C")));
 				continue;
 			}
 
 			if (!config->icells_mode && cell->type == "$lut") {
 				fprintf(f, ".names");
-				auto &inputs = cell->get("\\I");
+				auto &inputs = cell->getPort("\\I");
 				auto width = cell->parameters.at("\\WIDTH").as_int();
 				log_assert(inputs.size() == width);
 				for (int i = 0; i < inputs.size(); i++) {
 					fprintf(f, " %s", cstr(inputs.extract(i, 1)));
 				}
-				auto &output = cell->get("\\O");
+				auto &output = cell->getPort("\\O");
 				log_assert(output.size() == 1);
 				fprintf(f, " %s", cstr(output));
 				fprintf(f, "\n");
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 43c036690..d8a542347 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -389,8 +389,8 @@ struct BtorDumper
 			if(cell->type == "$assert")
 			{
 				log("writing assert cell - %s\n", cstr(cell->type));
-				const RTLIL::SigSpec* expr = &cell->get(RTLIL::IdString("\\A"));
-				const RTLIL::SigSpec* en = &cell->get(RTLIL::IdString("\\EN"));
+				const RTLIL::SigSpec* expr = &cell->getPort(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* en = &cell->getPort(RTLIL::IdString("\\EN"));
 				log_assert(expr->size() == 1);
 				log_assert(en->size() == 1);
 				int expr_line = dump_sigspec(expr, 1);
@@ -422,7 +422,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				w = w>output_width ? w:output_width; //padding of w
-				int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);				
+				int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w);				
 				int cell_line = l;
 				if(cell->type != "$pos")
 				{	
@@ -446,7 +446,7 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);
+				int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w);
 				if(cell->type == "$logic_not" && w > 1)
 				{
 					++line_num;
@@ -483,8 +483,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -517,8 +517,8 @@ struct BtorDumper
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type);
@@ -552,8 +552,8 @@ struct BtorDumper
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				//log_assert(l2_width <= ceil(log(l1_width)/log(2)) );
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
 				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
@@ -561,7 +561,7 @@ struct BtorDumper
 				if(l2_width > ceil(log(l1_width)/log(2)))
 				{
 					int extra_width = l2_width - ceil(log(l1_width)/log(2));
-					l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
+					l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 					++line_num;
 					str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
 					fprintf(f, "%s\n", str.c_str());
@@ -594,8 +594,8 @@ struct BtorDumper
 				log("writing binary cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output_width == 1);
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width);
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				if(l1_width >1)
@@ -630,9 +630,9 @@ struct BtorDumper
 			{
 				log("writing mux cell\n");
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
-				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
-				int s = dump_sigspec(&cell->get(RTLIL::IdString("\\S")), 1);
+				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), output_width);
+				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width);
+				int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
 					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
@@ -646,10 +646,10 @@ struct BtorDumper
 				log("writing cell - %s\n", cstr(cell->type));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				log(" - width is %d\n", output_width);
-				int cond = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
+				int cond = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				const RTLIL::SigSpec* cell_output = &cell->get(RTLIL::IdString("\\Q"));
-				int value = dump_sigspec(&cell->get(RTLIL::IdString("\\D")), output_width);
+				const RTLIL::SigSpec* cell_output = &cell->getPort(RTLIL::IdString("\\Q"));
+				int value = dump_sigspec(&cell->getPort(RTLIL::IdString("\\D")), output_width);
 				unsigned start_bit = 0;
 				for(unsigned i=0; i<cell_output->chunks().size(); ++i)
 				{
@@ -667,9 +667,9 @@ struct BtorDumper
 					}
 					if(cell->type == "$dffsr")
 					{
-						int sync_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\CLR")), 1);
+						int sync_reset = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLR")), 1);
 						bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool();
-						int sync_reset_value = dump_sigspec(&cell->get(RTLIL::IdString("\\SET")),
+						int sync_reset_value = dump_sigspec(&cell->getPort(RTLIL::IdString("\\SET")),
 							output_width);
 						bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
 						++line_num;
@@ -687,7 +687,7 @@ struct BtorDumper
 					int next = line_num;
 					if(cell->type == "$adff")
 					{
-						int async_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\ARST")), 1);
+						int async_reset = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ARST")), 1);
 						bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool();
 						int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
 							output_width, 0);
@@ -712,7 +712,7 @@ struct BtorDumper
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
 				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
@@ -724,13 +724,13 @@ struct BtorDumper
 				log("writing memwr cell\n");
 				if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
 					log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
-				int clk = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
+				int clk = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLK")), 1);
 				bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
-				int enable = dump_sigspec(&cell->get(RTLIL::IdString("\\EN")), 1);
+				int enable = dump_sigspec(&cell->getPort(RTLIL::IdString("\\EN")), 1);
 				int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
-				int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
+				int address = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
-				int data = dump_sigspec(&cell->get(RTLIL::IdString("\\DATA")), data_width);
+				int data = dump_sigspec(&cell->getPort(RTLIL::IdString("\\DATA")), data_width);
 				str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
 				int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
 				++line_num;
@@ -759,11 +759,11 @@ struct BtorDumper
 			else if(cell->type == "$slice")
 			{
 				log("writing slice cell\n");
-				const RTLIL::SigSpec* input = &cell->get(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input = &cell->getPort(RTLIL::IdString("\\A"));
 				int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input->size() == input_width);
 				int input_line = dump_sigspec(input, input_width);
-				const RTLIL::SigSpec* output = &cell->get(RTLIL::IdString("\\Y"));
+				const RTLIL::SigSpec* output = &cell->getPort(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
@@ -775,11 +775,11 @@ struct BtorDumper
 			else if(cell->type == "$concat")
 			{
 				log("writing concat cell\n");
-				const RTLIL::SigSpec* input_a = &cell->get(RTLIL::IdString("\\A"));
+				const RTLIL::SigSpec* input_a = &cell->getPort(RTLIL::IdString("\\A"));
 				int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				log_assert(input_a->size() == input_a_width);
 				int input_a_line = dump_sigspec(input_a, input_a_width);
-				const RTLIL::SigSpec* input_b = &cell->get(RTLIL::IdString("\\B"));
+				const RTLIL::SigSpec* input_b = &cell->getPort(RTLIL::IdString("\\B"));
 				int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
@@ -803,7 +803,7 @@ struct BtorDumper
 		const RTLIL::SigSpec *output_sig = nullptr;
 		if (cell->type == "$memrd")
 		{
-			output_sig = &cell->get(RTLIL::IdString("\\DATA"));
+			output_sig = &cell->getPort(RTLIL::IdString("\\DATA"));
 		}
 		else if(cell->type == "$memwr" || cell->type == "$assert")
 		{
@@ -811,11 +811,11 @@ struct BtorDumper
 		}
 		else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
 		{
-			output_sig = &cell->get(RTLIL::IdString("\\Q"));
+			output_sig = &cell->getPort(RTLIL::IdString("\\Q"));
 		}
 		else 
 		{
-			output_sig = &cell->get(RTLIL::IdString("\\Y"));
+			output_sig = &cell->getPort(RTLIL::IdString("\\Y"));
 		}
 		return output_sig;
 	}
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index ab5316ec3..a445e9cc9 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -79,8 +79,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 			for (RTLIL::Wire *wire : ports) {
 				log_assert(wire != NULL);
 				RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
-				if (cell->has(wire->name)) {
-					sig = sigmap(cell->get(wire->name));
+				if (cell->hasPort(wire->name)) {
+					sig = sigmap(cell->getPort(wire->name));
 					sig.extend(wire->width, false);
 				}
 				port_sigs.push_back(sig);
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 5826aea87..4bba32a63 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -305,17 +305,17 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_
 {
 	if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) {
 		fprintf(f, "$signed(");
-		dump_sigspec(f, cell->get("\\" + port));
+		dump_sigspec(f, cell->getPort("\\" + port));
 		fprintf(f, ")");
 	} else
-		dump_sigspec(f, cell->get("\\" + port));
+		dump_sigspec(f, cell->getPort("\\" + port));
 }
 
 std::string cellname(RTLIL::Cell *cell)
 {
-	if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->has("\\Q"))
+	if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->hasPort("\\Q"))
 	{
-		RTLIL::SigSpec sig = cell->get("\\Q");
+		RTLIL::SigSpec sig = cell->getPort("\\Q");
 		if (SIZE(sig) != 1 || sig.is_fully_const())
 			goto no_special_reg_name;
 
@@ -350,7 +350,7 @@ no_special_reg_name:
 void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op)
 {
 	fprintf(f, "%s" "assign ", indent.c_str());
-	dump_sigspec(f, cell->get("\\Y"));
+	dump_sigspec(f, cell->getPort("\\Y"));
 	fprintf(f, " = %s ", op.c_str());
 	dump_attributes(f, "", cell->attributes, ' ');
 	dump_cell_expr_port(f, cell, "A", true);
@@ -360,7 +360,7 @@ void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s
 void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op)
 {
 	fprintf(f, "%s" "assign ", indent.c_str());
-	dump_sigspec(f, cell->get("\\Y"));
+	dump_sigspec(f, cell->getPort("\\Y"));
 	fprintf(f, " = ");
 	dump_cell_expr_port(f, cell, "A", true);
 	fprintf(f, " %s ", op.c_str());
@@ -373,7 +373,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 {
 	if (cell->type == "$_INV_") {
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->get("\\Y"));
+		dump_sigspec(f, cell->getPort("\\Y"));
 		fprintf(f, " = ");
 		fprintf(f, "~");
 		dump_attributes(f, "", cell->attributes, ' ');
@@ -384,7 +384,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 	if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->get("\\Y"));
+		dump_sigspec(f, cell->getPort("\\Y"));
 		fprintf(f, " = ");
 		dump_cell_expr_port(f, cell, "A", false);
 		fprintf(f, " ");
@@ -403,7 +403,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 	if (cell->type == "$_MUX_") {
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->get("\\Y"));
+		dump_sigspec(f, cell->getPort("\\Y"));
 		fprintf(f, " = ");
 		dump_cell_expr_port(f, cell, "S", false);
 		fprintf(f, " ? ");
@@ -418,23 +418,23 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type.substr(0, 6) == "$_DFF_")
 	{
 		std::string reg_name = cellname(cell);
-		bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
+		bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
 
 		if (!out_is_reg_wire)
 			fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str());
 
 		dump_attributes(f, indent, cell->attributes);
 		fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg");
-		dump_sigspec(f, cell->get("\\C"));
+		dump_sigspec(f, cell->getPort("\\C"));
 		if (cell->type[7] != '_') {
 			fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg");
-			dump_sigspec(f, cell->get("\\R"));
+			dump_sigspec(f, cell->getPort("\\R"));
 		}
 		fprintf(f, ")\n");
 
 		if (cell->type[7] != '_') {
 			fprintf(f, "%s" "  if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!");
-			dump_sigspec(f, cell->get("\\R"));
+			dump_sigspec(f, cell->getPort("\\R"));
 			fprintf(f, ")\n");
 			fprintf(f, "%s" "    %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]);
 			fprintf(f, "%s" "  else\n", indent.c_str());
@@ -446,7 +446,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 		if (!out_is_reg_wire) {
 			fprintf(f, "%s" "assign ", indent.c_str());
-			dump_sigspec(f, cell->get("\\Q"));
+			dump_sigspec(f, cell->getPort("\\Q"));
 			fprintf(f, " = %s;\n", reg_name.c_str());
 		}
 
@@ -458,27 +458,27 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 		char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10];
 
 		std::string reg_name = cellname(cell);
-		bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
+		bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
 
 		if (!out_is_reg_wire)
 			fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str());
 
 		dump_attributes(f, indent, cell->attributes);
 		fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg");
-		dump_sigspec(f, cell->get("\\C"));
+		dump_sigspec(f, cell->getPort("\\C"));
 		fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg");
-		dump_sigspec(f, cell->get("\\S"));
+		dump_sigspec(f, cell->getPort("\\S"));
 		fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg");
-		dump_sigspec(f, cell->get("\\R"));
+		dump_sigspec(f, cell->getPort("\\R"));
 		fprintf(f, ")\n");
 
 		fprintf(f, "%s" "  if (%s", indent.c_str(), pol_r == 'P' ? "" : "!");
-		dump_sigspec(f, cell->get("\\R"));
+		dump_sigspec(f, cell->getPort("\\R"));
 		fprintf(f, ")\n");
 		fprintf(f, "%s" "    %s <= 0;\n", indent.c_str(), reg_name.c_str());
 
 		fprintf(f, "%s" "  else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!");
-		dump_sigspec(f, cell->get("\\S"));
+		dump_sigspec(f, cell->getPort("\\S"));
 		fprintf(f, ")\n");
 		fprintf(f, "%s" "    %s <= 1;\n", indent.c_str(), reg_name.c_str());
 
@@ -489,7 +489,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 		if (!out_is_reg_wire) {
 			fprintf(f, "%s" "assign ", indent.c_str());
-			dump_sigspec(f, cell->get("\\Q"));
+			dump_sigspec(f, cell->getPort("\\Q"));
 			fprintf(f, " = %s;\n", reg_name.c_str());
 		}
 
@@ -547,7 +547,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe")
 	{
 		int width = cell->parameters["\\WIDTH"].as_int();
-		int s_width = cell->get("\\S").size();
+		int s_width = cell->getPort("\\S").size();
 		std::string func_name = cellname(cell);
 
 		fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str());
@@ -579,13 +579,13 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 		fprintf(f, "%s" "endfunction\n", indent.c_str());
 
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->get("\\Y"));
+		dump_sigspec(f, cell->getPort("\\Y"));
 		fprintf(f, " = %s(", func_name.c_str());
-		dump_sigspec(f, cell->get("\\A"));
+		dump_sigspec(f, cell->getPort("\\A"));
 		fprintf(f, ", ");
-		dump_sigspec(f, cell->get("\\B"));
+		dump_sigspec(f, cell->getPort("\\B"));
 		fprintf(f, ", ");
-		dump_sigspec(f, cell->get("\\S"));
+		dump_sigspec(f, cell->getPort("\\S"));
 		fprintf(f, ");\n");
 		return true;
 	}
@@ -593,9 +593,9 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type == "$slice")
 	{
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->get("\\Y"));
+		dump_sigspec(f, cell->getPort("\\Y"));
 		fprintf(f, " = ");
-		dump_sigspec(f, cell->get("\\A"));
+		dump_sigspec(f, cell->getPort("\\A"));
 		fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int());
 		return true;
 	}
@@ -603,14 +603,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type == "$bu0")
 	{
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->get("\\Y"));
+		dump_sigspec(f, cell->getPort("\\Y"));
 		if (cell->parameters["\\A_SIGNED"].as_bool()) {
 			fprintf(f, " = $signed(");
-			dump_sigspec(f, cell->get("\\A"));
+			dump_sigspec(f, cell->getPort("\\A"));
 			fprintf(f, ");\n");
 		} else {
 			fprintf(f, " = { 1'b0, ");
-			dump_sigspec(f, cell->get("\\A"));
+			dump_sigspec(f, cell->getPort("\\A"));
 			fprintf(f, " };\n");
 		}
 		return true;
@@ -619,11 +619,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 	if (cell->type == "$concat")
 	{
 		fprintf(f, "%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->get("\\Y"));
+		dump_sigspec(f, cell->getPort("\\Y"));
 		fprintf(f, " = { ");
-		dump_sigspec(f, cell->get("\\B"));
+		dump_sigspec(f, cell->getPort("\\B"));
 		fprintf(f, " , ");
-		dump_sigspec(f, cell->get("\\A"));
+		dump_sigspec(f, cell->getPort("\\A"));
 		fprintf(f, " };\n");
 		return true;
 	}
@@ -633,17 +633,17 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 		RTLIL::SigSpec sig_clk, sig_arst, val_arst;
 		bool pol_clk, pol_arst = false;
 
-		sig_clk = cell->get("\\CLK");
+		sig_clk = cell->getPort("\\CLK");
 		pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool();
 
 		if (cell->type == "$adff") {
-			sig_arst = cell->get("\\ARST");
+			sig_arst = cell->getPort("\\ARST");
 			pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool();
 			val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]);
 		}
 
 		std::string reg_name = cellname(cell);
-		bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
+		bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
 
 		if (!out_is_reg_wire)
 			fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
@@ -672,7 +672,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
 
 		if (!out_is_reg_wire) {
 			fprintf(f, "%s" "assign ", indent.c_str());
-			dump_sigspec(f, cell->get("\\Q"));
+			dump_sigspec(f, cell->getPort("\\Q"));
 			fprintf(f, " = %s;\n", reg_name.c_str());
 		}
 
@@ -920,10 +920,10 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
 		for (auto &it : module->cells_)
 		{
 			RTLIL::Cell *cell = it.second;
-			if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q"))
+			if (!reg_ct.cell_known(cell->type) || !cell->hasPort("\\Q"))
 				continue;
 
-			RTLIL::SigSpec sig = cell->get("\\Q");
+			RTLIL::SigSpec sig = cell->getPort("\\Q");
 
 			if (sig.is_chunk()) {
 				RTLIL::SigChunk chunk = sig.as_chunk();
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 0cc4f4c47..f4f82823b 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -61,10 +61,10 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 
 	cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
 	cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
-	cell->set("\\A", arg);
+	cell->setPort("\\A", arg);
 
 	cell->parameters["\\Y_WIDTH"] = result_width;
-	cell->set("\\Y", wire);
+	cell->setPort("\\Y", wire);
 	return wire;
 }
 
@@ -95,10 +95,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 
 	cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
 	cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
-	cell->set("\\A", sig);
+	cell->setPort("\\A", sig);
 
 	cell->parameters["\\Y_WIDTH"] = width;
-	cell->set("\\Y", wire);
+	cell->setPort("\\Y", wire);
 	sig = wire;
 }
 
@@ -127,11 +127,11 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 	cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
 	cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
 
-	cell->set("\\A", left);
-	cell->set("\\B", right);
+	cell->setPort("\\A", left);
+	cell->setPort("\\B", right);
 
 	cell->parameters["\\Y_WIDTH"] = result_width;
-	cell->set("\\Y", wire);
+	cell->setPort("\\Y", wire);
 	return wire;
 }
 
@@ -158,10 +158,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 
 	cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
 
-	cell->set("\\A", right);
-	cell->set("\\B", left);
-	cell->set("\\S", cond);
-	cell->set("\\Y", wire);
+	cell->setPort("\\A", right);
+	cell->setPort("\\B", left);
+	cell->setPort("\\S", cond);
+	cell->setPort("\\Y", wire);
 
 	return wire;
 }
@@ -1203,9 +1203,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			while ((1 << addr_bits) < current_module->memories[str]->size)
 				addr_bits++;
 
-			cell->set("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
-			cell->set("\\ADDR", children[0]->genWidthRTLIL(addr_bits));
-			cell->set("\\DATA", RTLIL::SigSpec(wire));
+			cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
+			cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits));
+			cell->setPort("\\DATA", RTLIL::SigSpec(wire));
 
 			cell->parameters["\\MEMID"] = RTLIL::Const(str);
 			cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
@@ -1231,10 +1231,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			while ((1 << addr_bits) < current_module->memories[str]->size)
 				addr_bits++;
 
-			cell->set("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
-			cell->set("\\ADDR", children[0]->genWidthRTLIL(addr_bits));
-			cell->set("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width));
-			cell->set("\\EN", children[2]->genRTLIL());
+			cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
+			cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits));
+			cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width));
+			cell->setPort("\\EN", children[2]->genRTLIL());
 
 			cell->parameters["\\MEMID"] = RTLIL::Const(str);
 			cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
@@ -1271,8 +1271,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
 
-			cell->set("\\A", check);
-			cell->set("\\EN", en);
+			cell->setPort("\\A", check);
+			cell->setPort("\\EN", en);
 		}
 		break;
 
@@ -1331,9 +1331,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					if (child->str.size() == 0) {
 						char buf[100];
 						snprintf(buf, 100, "$%d", ++port_counter);
-						cell->set(buf, sig);
+						cell->setPort(buf, sig);
 					} else {
-						cell->set(child->str, sig);
+						cell->setPort(child->str, sig);
 					}
 					continue;
 				}
diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index 67cc7da78..f696140eb 100644
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -207,9 +207,9 @@ cell_body:
 		delete $5;
 	} |
 	cell_body TOK_CONNECT TOK_ID sigspec EOL {
-		if (current_cell->has($3))
+		if (current_cell->hasPort($3))
 			rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());
-		current_cell->set($3, *$4);
+		current_cell->setPort($3, *$4);
 		delete $4;
 		free($3);
 	} |
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index d3168ab8e..72e370b94 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -56,36 +56,36 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
 static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
 {
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
-	cell->set("\\A", A);
-	cell->set("\\Y", module->addWire(NEW_ID));
-	return cell->get("\\Y");
+	cell->setPort("\\A", A);
+	cell->setPort("\\Y", module->addWire(NEW_ID));
+	return cell->getPort("\\Y");
 }
 
 static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
-	cell->set("\\A", A);
-	cell->set("\\B", B);
-	cell->set("\\Y", module->addWire(NEW_ID));
-	return cell->get("\\Y");
+	cell->setPort("\\A", A);
+	cell->setPort("\\B", B);
+	cell->setPort("\\Y", module->addWire(NEW_ID));
+	return cell->getPort("\\Y");
 }
 
 static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
-	cell->set("\\A", A);
-	cell->set("\\B", B);
-	cell->set("\\Y", module->addWire(NEW_ID));
-	return cell->get("\\Y");
+	cell->setPort("\\A", A);
+	cell->setPort("\\B", B);
+	cell->setPort("\\Y", module->addWire(NEW_ID));
+	return cell->getPort("\\Y");
 }
 
 static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
 {
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
-	cell->set("\\A", A);
-	cell->set("\\B", B);
-	cell->set("\\Y", module->addWire(NEW_ID));
-	return cell->get("\\Y");
+	cell->setPort("\\A", A);
+	cell->setPort("\\B", B);
+	cell->setPort("\\Y", module->addWire(NEW_ID));
+	return cell->getPort("\\Y");
 }
 
 static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack, token_t next_token)
@@ -241,18 +241,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 		rerun_invert_rollback = false;
 
 		for (auto &it : module->cells_) {
-			if (it.second->type == "$_INV_" && it.second->get("\\Y") == clk_sig) {
-				clk_sig = it.second->get("\\A");
+			if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == clk_sig) {
+				clk_sig = it.second->getPort("\\A");
 				clk_polarity = !clk_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_INV_" && it.second->get("\\Y") == clear_sig) {
-				clear_sig = it.second->get("\\A");
+			if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == clear_sig) {
+				clear_sig = it.second->getPort("\\A");
 				clear_polarity = !clear_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_INV_" && it.second->get("\\Y") == preset_sig) {
-				preset_sig = it.second->get("\\A");
+			if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == preset_sig) {
+				preset_sig = it.second->getPort("\\A");
 				preset_polarity = !preset_polarity;
 				rerun_invert_rollback = true;
 			}
@@ -260,13 +260,13 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 	}
 
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
-	cell->set("\\A", iq_sig);
-	cell->set("\\Y", iqn_sig);
+	cell->setPort("\\A", iq_sig);
+	cell->setPort("\\Y", iqn_sig);
 
 	cell = module->addCell(NEW_ID, "");
-	cell->set("\\D", data_sig);
-	cell->set("\\Q", iq_sig);
-	cell->set("\\C", clk_sig);
+	cell->setPort("\\D", data_sig);
+	cell->setPort("\\Q", iq_sig);
+	cell->setPort("\\C", clk_sig);
 
 	if (clear_sig.size() == 0 && preset_sig.size() == 0) {
 		cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
@@ -274,18 +274,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
 
 	if (clear_sig.size() == 1 && preset_sig.size() == 0) {
 		cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
-		cell->set("\\R", clear_sig);
+		cell->setPort("\\R", clear_sig);
 	}
 
 	if (clear_sig.size() == 0 && preset_sig.size() == 1) {
 		cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
-		cell->set("\\R", preset_sig);
+		cell->setPort("\\R", preset_sig);
 	}
 
 	if (clear_sig.size() == 1 && preset_sig.size() == 1) {
 		cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
-		cell->set("\\S", preset_sig);
-		cell->set("\\R", clear_sig);
+		cell->setPort("\\S", preset_sig);
+		cell->setPort("\\R", clear_sig);
 	}
 
 	log_assert(!cell->type.empty());
@@ -318,18 +318,18 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
 		rerun_invert_rollback = false;
 
 		for (auto &it : module->cells_) {
-			if (it.second->type == "$_INV_" && it.second->get("\\Y") == enable_sig) {
-				enable_sig = it.second->get("\\A");
+			if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == enable_sig) {
+				enable_sig = it.second->getPort("\\A");
 				enable_polarity = !enable_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_INV_" && it.second->get("\\Y") == clear_sig) {
-				clear_sig = it.second->get("\\A");
+			if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == clear_sig) {
+				clear_sig = it.second->getPort("\\A");
 				clear_polarity = !clear_polarity;
 				rerun_invert_rollback = true;
 			}
-			if (it.second->type == "$_INV_" && it.second->get("\\Y") == preset_sig) {
-				preset_sig = it.second->get("\\A");
+			if (it.second->type == "$_INV_" && it.second->getPort("\\Y") == preset_sig) {
+				preset_sig = it.second->getPort("\\A");
 				preset_polarity = !preset_polarity;
 				rerun_invert_rollback = true;
 			}
@@ -337,8 +337,8 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
 	}
 
 	RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
-	cell->set("\\A", iq_sig);
-	cell->set("\\Y", iqn_sig);
+	cell->setPort("\\A", iq_sig);
+	cell->setPort("\\Y", iqn_sig);
 
 	if (clear_sig.size() == 1)
 	{
@@ -348,24 +348,24 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
 		if (clear_polarity == true || clear_polarity != enable_polarity)
 		{
 			RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
-			inv->set("\\A", clear_sig);
-			inv->set("\\Y", module->addWire(NEW_ID));
+			inv->setPort("\\A", clear_sig);
+			inv->setPort("\\Y", module->addWire(NEW_ID));
 
 			if (clear_polarity == true)
-				clear_negative = inv->get("\\Y");
+				clear_negative = inv->getPort("\\Y");
 			if (clear_polarity != enable_polarity)
-				clear_enable = inv->get("\\Y");
+				clear_enable = inv->getPort("\\Y");
 		}
 
 		RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
-		data_gate->set("\\A", data_sig);
-		data_gate->set("\\B", clear_negative);
-		data_gate->set("\\Y", data_sig = module->addWire(NEW_ID));
+		data_gate->setPort("\\A", data_sig);
+		data_gate->setPort("\\B", clear_negative);
+		data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
 
 		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
-		enable_gate->set("\\A", enable_sig);
-		enable_gate->set("\\B", clear_enable);
-		enable_gate->set("\\Y", data_sig = module->addWire(NEW_ID));
+		enable_gate->setPort("\\A", enable_sig);
+		enable_gate->setPort("\\B", clear_enable);
+		enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
 	}
 
 	if (preset_sig.size() == 1)
@@ -376,30 +376,30 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
 		if (preset_polarity == false || preset_polarity != enable_polarity)
 		{
 			RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
-			inv->set("\\A", preset_sig);
-			inv->set("\\Y", module->addWire(NEW_ID));
+			inv->setPort("\\A", preset_sig);
+			inv->setPort("\\Y", module->addWire(NEW_ID));
 
 			if (preset_polarity == false)
-				preset_positive = inv->get("\\Y");
+				preset_positive = inv->getPort("\\Y");
 			if (preset_polarity != enable_polarity)
-				preset_enable = inv->get("\\Y");
+				preset_enable = inv->getPort("\\Y");
 		}
 
 		RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
-		data_gate->set("\\A", data_sig);
-		data_gate->set("\\B", preset_positive);
-		data_gate->set("\\Y", data_sig = module->addWire(NEW_ID));
+		data_gate->setPort("\\A", data_sig);
+		data_gate->setPort("\\B", preset_positive);
+		data_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
 
 		RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
-		enable_gate->set("\\A", enable_sig);
-		enable_gate->set("\\B", preset_enable);
-		enable_gate->set("\\Y", data_sig = module->addWire(NEW_ID));
+		enable_gate->setPort("\\A", enable_sig);
+		enable_gate->setPort("\\B", preset_enable);
+		enable_gate->setPort("\\Y", data_sig = module->addWire(NEW_ID));
 	}
 
 	cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
-	cell->set("\\D", data_sig);
-	cell->set("\\Q", iq_sig);
-	cell->set("\\E", enable_sig);
+	cell->setPort("\\D", data_sig);
+	cell->setPort("\\Q", iq_sig);
+	cell->setPort("\\E", enable_sig);
 }
 
 struct LibertyFrontend : public Frontend {
diff --git a/kernel/consteval.h b/kernel/consteval.h
index e5cae1022..529d8962d 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -87,22 +87,22 @@ struct ConstEval
 	{
 		RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-		log_assert(cell->has("\\Y"));
-		sig_y = values_map(assign_map(cell->get("\\Y")));
+		log_assert(cell->hasPort("\\Y"));
+		sig_y = values_map(assign_map(cell->getPort("\\Y")));
 		if (sig_y.is_fully_const())
 			return true;
 
-		if (cell->has("\\S")) {
-			sig_s = cell->get("\\S");
+		if (cell->hasPort("\\S")) {
+			sig_s = cell->getPort("\\S");
 			if (!eval(sig_s, undef, cell))
 				return false;
 		}
 
-		if (cell->has("\\A"))
-			sig_a = cell->get("\\A");
+		if (cell->hasPort("\\A"))
+			sig_a = cell->getPort("\\A");
 
-		if (cell->has("\\B"))
-			sig_b = cell->get("\\B");
+		if (cell->hasPort("\\B"))
+			sig_b = cell->getPort("\\B");
 
 		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")
 		{
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 28de216cd..012253144 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -447,9 +447,9 @@ namespace {
 
 		void port(const char *name, int width)
 		{
-			if (!cell->has(name))
+			if (!cell->hasPort(name))
 				error(__LINE__);
-			if (cell->get(name).size() != width)
+			if (cell->getPort(name).size() != width)
 				error(__LINE__);
 			expected_ports.insert(name);
 		}
@@ -478,9 +478,9 @@ namespace {
 
 			for (const char *p = ports; *p; p++) {
 				char portname[3] = { '\\', *p, 0 };
-				if (!cell->has(portname))
+				if (!cell->hasPort(portname))
 					error(__LINE__);
-				if (cell->get(portname).size() != 1)
+				if (cell->getPort(portname).size() != 1)
 					error(__LINE__);
 			}
 
@@ -1001,7 +1001,7 @@ namespace {
 #if 0
 void RTLIL::Module::remove(RTLIL::Wire *wire)
 {
-	std::set<RTLIL::Wire*> wires_;
+	std::setPort<RTLIL::Wire*> wires_;
 	wires_.insert(wire);
 	remove(wires_);
 }
@@ -1167,8 +1167,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
 		cell->parameters["\\A_SIGNED"] = is_signed;         \
 		cell->parameters["\\A_WIDTH"] = sig_a.size();        \
 		cell->parameters["\\Y_WIDTH"] = sig_y.size();        \
-		cell->set("\\A", sig_a);                   \
-		cell->set("\\Y", sig_y);                   \
+		cell->setPort("\\A", sig_a);                   \
+		cell->setPort("\\Y", sig_y);                   \
 		return cell;                                        \
 	} \
 	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
@@ -1196,9 +1196,9 @@ DEF_METHOD(LogicNot,   1, "$logic_not")
 		cell->parameters["\\A_WIDTH"] = sig_a.size();        \
 		cell->parameters["\\B_WIDTH"] = sig_b.size();        \
 		cell->parameters["\\Y_WIDTH"] = sig_y.size();        \
-		cell->set("\\A", sig_a);                   \
-		cell->set("\\B", sig_b);                   \
-		cell->set("\\Y", sig_y);                   \
+		cell->setPort("\\A", sig_a);                   \
+		cell->setPort("\\B", sig_b);                   \
+		cell->setPort("\\Y", sig_y);                   \
 		return cell;                                        \
 	} \
 	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
@@ -1239,10 +1239,10 @@ DEF_METHOD(LogicOr,  1, "$logic_or")
 		cell->parameters["\\WIDTH"] = sig_a.size();               \
 		cell->parameters["\\WIDTH"] = sig_b.size();               \
 		if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size();  \
-		cell->set("\\A", sig_a);                        \
-		cell->set("\\B", sig_b);                        \
-		cell->set("\\S", sig_s);                        \
-		cell->set("\\Y", sig_y);                        \
+		cell->setPort("\\A", sig_a);                        \
+		cell->setPort("\\B", sig_b);                        \
+		cell->setPort("\\S", sig_s);                        \
+		cell->setPort("\\Y", sig_y);                        \
 		return cell;                                             \
 	} \
 	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
@@ -1258,8 +1258,8 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 #define DEF_METHOD_2(_func, _type, _P1, _P2) \
 	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
 		RTLIL::Cell *cell = addCell(name, _type);   \
-		cell->set("\\" #_P1, sig1);                 \
-		cell->set("\\" #_P2, sig2);                 \
+		cell->setPort("\\" #_P1, sig1);                 \
+		cell->setPort("\\" #_P2, sig2);                 \
 		return cell;                                \
 	} \
 	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
@@ -1270,9 +1270,9 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 #define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
 	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
 		RTLIL::Cell *cell = addCell(name, _type);   \
-		cell->set("\\" #_P1, sig1);                 \
-		cell->set("\\" #_P2, sig2);                 \
-		cell->set("\\" #_P3, sig3);                 \
+		cell->setPort("\\" #_P1, sig1);                 \
+		cell->setPort("\\" #_P2, sig2);                 \
+		cell->setPort("\\" #_P3, sig3);                 \
 		return cell;                                \
 	} \
 	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
@@ -1283,10 +1283,10 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 #define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
 	RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
 		RTLIL::Cell *cell = addCell(name, _type);   \
-		cell->set("\\" #_P1, sig1);                 \
-		cell->set("\\" #_P2, sig2);                 \
-		cell->set("\\" #_P3, sig3);                 \
-		cell->set("\\" #_P4, sig4);                 \
+		cell->setPort("\\" #_P1, sig1);                 \
+		cell->setPort("\\" #_P2, sig2);                 \
+		cell->setPort("\\" #_P3, sig3);                 \
+		cell->setPort("\\" #_P4, sig4);                 \
 		return cell;                                \
 	} \
 	RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
@@ -1311,9 +1311,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\B_WIDTH"] = sig_b.size();
 	cell->parameters["\\Y_WIDTH"] = sig_y.size();
-	cell->set("\\A", sig_a);
-	cell->set("\\B", sig_b);
-	cell->set("\\Y", sig_y);
+	cell->setPort("\\A", sig_a);
+	cell->setPort("\\B", sig_b);
+	cell->setPort("\\Y", sig_y);
 	return cell;
 }
 
@@ -1323,8 +1323,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a,
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\Y_WIDTH"] = sig_y.size();
 	cell->parameters["\\OFFSET"] = offset;
-	cell->set("\\A", sig_a);
-	cell->set("\\Y", sig_y);
+	cell->setPort("\\A", sig_a);
+	cell->setPort("\\Y", sig_y);
 	return cell;
 }
 
@@ -1333,9 +1333,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a
 	RTLIL::Cell *cell = addCell(name, "$concat");
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\B_WIDTH"] = sig_b.size();
-	cell->set("\\A", sig_a);
-	cell->set("\\B", sig_b);
-	cell->set("\\Y", sig_y);
+	cell->setPort("\\A", sig_a);
+	cell->setPort("\\B", sig_b);
+	cell->setPort("\\Y", sig_y);
 	return cell;
 }
 
@@ -1344,16 +1344,16 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
 	RTLIL::Cell *cell = addCell(name, "$lut");
 	cell->parameters["\\LUT"] = lut;
 	cell->parameters["\\WIDTH"] = sig_i.size();
-	cell->set("\\I", sig_i);
-	cell->set("\\O", sig_o);
+	cell->setPort("\\I", sig_i);
+	cell->setPort("\\O", sig_o);
 	return cell;
 }
 
 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
 {
 	RTLIL::Cell *cell = addCell(name, "$assert");
-	cell->set("\\A", sig_a);
-	cell->set("\\EN", sig_en);
+	cell->setPort("\\A", sig_a);
+	cell->setPort("\\EN", sig_en);
 	return cell;
 }
 
@@ -1363,9 +1363,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set,
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->set("\\SET", sig_set);
-	cell->set("\\CLR", sig_clr);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\SET", sig_set);
+	cell->setPort("\\CLR", sig_clr);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1374,9 +1374,9 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk,
 	RTLIL::Cell *cell = addCell(name, "$dff");
 	cell->parameters["\\CLK_POLARITY"] = clk_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->set("\\CLK", sig_clk);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\CLK", sig_clk);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1388,11 +1388,11 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->set("\\CLK", sig_clk);
-	cell->set("\\SET", sig_set);
-	cell->set("\\CLR", sig_clr);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\CLK", sig_clk);
+	cell->setPort("\\SET", sig_set);
+	cell->setPort("\\CLR", sig_clr);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1404,10 +1404,10 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk
 	cell->parameters["\\ARST_POLARITY"] = arst_polarity;
 	cell->parameters["\\ARST_VALUE"] = arst_value;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->set("\\CLK", sig_clk);
-	cell->set("\\ARST", sig_arst);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\CLK", sig_clk);
+	cell->setPort("\\ARST", sig_arst);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1416,9 +1416,9 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e
 	RTLIL::Cell *cell = addCell(name, "$dlatch");
 	cell->parameters["\\EN_POLARITY"] = en_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->set("\\EN", sig_en);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\EN", sig_en);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1430,20 +1430,20 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->set("\\EN", sig_en);
-	cell->set("\\SET", sig_set);
-	cell->set("\\CLR", sig_clr);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\EN", sig_en);
+	cell->setPort("\\SET", sig_set);
+	cell->setPort("\\CLR", sig_clr);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
 RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
 {
 	RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
-	cell->set("\\C", sig_clk);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\C", sig_clk);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1451,11 +1451,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si
 		RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
 {
 	RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
-	cell->set("\\C", sig_clk);
-	cell->set("\\S", sig_set);
-	cell->set("\\R", sig_clr);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\C", sig_clk);
+	cell->setPort("\\S", sig_set);
+	cell->setPort("\\R", sig_clr);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1463,19 +1463,19 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig
 		bool arst_value, bool clk_polarity, bool arst_polarity)
 {
 	RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
-	cell->set("\\C", sig_clk);
-	cell->set("\\R", sig_arst);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\C", sig_clk);
+	cell->setPort("\\R", sig_arst);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
 RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
 {
 	RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
-	cell->set("\\E", sig_en);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\E", sig_en);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1483,11 +1483,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
 		RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
 {
 	RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
-	cell->set("\\E", sig_en);
-	cell->set("\\S", sig_set);
-	cell->set("\\R", sig_clr);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
+	cell->setPort("\\E", sig_en);
+	cell->setPort("\\S", sig_set);
+	cell->setPort("\\R", sig_clr);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
 	return cell;
 }
 
@@ -1509,12 +1509,12 @@ RTLIL::Memory::Memory()
 	size = 0;
 }
 
-bool RTLIL::Cell::has(RTLIL::IdString portname) const
+bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
 {
 	return connections_.count(portname) != 0;
 }
 
-void RTLIL::Cell::unset(RTLIL::IdString portname)
+void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
 {
 	std::pair<RTLIL::IdString, RTLIL::SigSpec> new_conn(portname, RTLIL::SigSpec());
 
@@ -1528,7 +1528,7 @@ void RTLIL::Cell::unset(RTLIL::IdString portname)
 	connections_.erase(portname);
 }
 
-void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
+void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
 {
 	std::pair<RTLIL::IdString, RTLIL::SigSpec> new_conn(portname, signal);
 
@@ -1542,7 +1542,7 @@ void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
 	connections_[portname] = signal;
 }
 
-const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const
+const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
 {
 	return connections_.at(portname);
 }
@@ -1552,6 +1552,26 @@ const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() cons
 	return connections_;
 }
 
+bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
+{
+	return parameters.count(paramname);
+}
+
+void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
+{
+	parameters.erase(paramname);
+}
+
+void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
+{
+	parameters[paramname] = value;
+}
+
+const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
+{
+	return parameters.at(paramname);
+}
+
 void RTLIL::Cell::check()
 {
 #ifndef NDEBUG
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 5107e5f2b..796d45df1 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -331,6 +331,7 @@ struct RTLIL::Selection
 
 struct RTLIL::Monitor
 {
+	virtual ~Monitor() { }
 	virtual void notify_module_add(RTLIL::Module*) { }
 	virtual void notify_module_del(RTLIL::Module*) { }
 	virtual void notify_cell_connect(RTLIL::Cell*, const std::pair<RTLIL::IdString, RTLIL::SigSpec>&) { }
@@ -663,12 +664,18 @@ public:
 	RTLIL_ATTRIBUTE_MEMBERS
 
 	// access cell ports
-	bool has(RTLIL::IdString portname) const;
-	void unset(RTLIL::IdString portname);
-	void set(RTLIL::IdString portname, RTLIL::SigSpec signal);
-	const RTLIL::SigSpec &get(RTLIL::IdString portname) const;
+	bool hasPort(RTLIL::IdString portname) const;
+	void unsetPort(RTLIL::IdString portname);
+	void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
+	const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
 	const std::map<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
 
+	// access cell parameters
+	bool hasParam(RTLIL::IdString portname) const;
+	void unsetParam(RTLIL::IdString portname);
+	void setParam(RTLIL::IdString portname, RTLIL::Const value);
+	const RTLIL::Const &getParam(RTLIL::IdString portname) const;
+
 	void check();
 	void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);
 
diff --git a/kernel/satgen.h b/kernel/satgen.h
index ce2c90280..1ada1e16a 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -182,9 +182,9 @@ struct SatGen
 
 		if (model_undef && (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || is_arith_compare))
 		{
-			std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
+			std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 			if (is_arith_compare)
 				extendSignalWidth(undef_a, undef_b, cell, true);
 			else
@@ -195,7 +195,7 @@ struct SatGen
 			int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
 
 			if (cell->type == "$div" || cell->type == "$mod") {
-				std::vector<int> b = importSigSpec(cell->get("\\B"), timestep);
+				std::vector<int> b = importSigSpec(cell->getPort("\\B"), timestep);
 				undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
 			}
 
@@ -215,9 +215,9 @@ struct SatGen
 				cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
 				cell->type == "$add" || cell->type == "$sub")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -237,9 +237,9 @@ struct SatGen
 
 			if (model_undef && !arith_undef_handled)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
 
 				if (cell->type == "$and" || cell->type == "$_AND_") {
@@ -265,7 +265,7 @@ struct SatGen
 			}
 			else if (model_undef)
 			{
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -273,16 +273,16 @@ struct SatGen
 
 		if (cell->type == "$_INV_" || cell->type == "$not")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			ez->assume(ez->vec_eq(ez->vec_not(a), yy));
 
 			if (model_undef) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell, true);
 				ez->assume(ez->vec_eq(undef_a, undef_y));
 				undefGating(y, yy, undef_y);
@@ -292,20 +292,20 @@ struct SatGen
 
 		if (cell->type == "$_MUX_" || cell->type == "$mux")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> s = importDefSigSpec(cell->get("\\S"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
+			std::vector<int> s = importDefSigSpec(cell->getPort("\\S"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_s = importUndefSigSpec(cell->get("\\S"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
+				std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 
 				std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
 				std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
@@ -318,10 +318,10 @@ struct SatGen
 
 		if (cell->type == "$pmux" || cell->type == "$safe_pmux")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> s = importDefSigSpec(cell->get("\\S"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
+			std::vector<int> s = importDefSigSpec(cell->getPort("\\S"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -336,10 +336,10 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_s = importUndefSigSpec(cell->get("\\S"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
+				std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 
 				int maybe_one_hot = ez->FALSE;
 				int maybe_many_hot = ez->FALSE;
@@ -387,8 +387,8 @@ struct SatGen
 
 		if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -402,8 +402,8 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0");
 
 				if (cell->type == "$pos" || cell->type == "$bu0") {
@@ -422,8 +422,8 @@ struct SatGen
 		if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
 				cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -442,8 +442,8 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				int aX = ez->expression(ezSAT::OpOr, undef_a);
 
 				if (cell->type == "$reduce_and") {
@@ -469,12 +469,12 @@ struct SatGen
 
 		if (cell->type == "$logic_and" || cell->type == "$logic_or")
 		{
-			std::vector<int> vec_a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> vec_b = importDefSigSpec(cell->get("\\B"), timestep);
+			std::vector<int> vec_a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> vec_b = importDefSigSpec(cell->getPort("\\B"), timestep);
 
 			int a = ez->expression(ez->OpOr, vec_a);
 			int b = ez->expression(ez->OpOr, vec_b);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -487,9 +487,9 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 
 				int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
 				int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
@@ -516,16 +516,16 @@ struct SatGen
 		if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt")
 		{
 			bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 			extendSignalWidth(a, b, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
 			if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 				a = ez->vec_or(a, undef_a);
 				b = ez->vec_or(b, undef_b);
@@ -548,9 +548,9 @@ struct SatGen
 
 			if (model_undef && (cell->type == "$eqx" || cell->type == "$nex"))
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 
 				if (cell->type == "$eqx")
@@ -565,9 +565,9 @@ struct SatGen
 			}
 			else if (model_undef && (cell->type == "$eq" || cell->type == "$ne"))
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 
 				int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@@ -589,7 +589,7 @@ struct SatGen
 			else
 			{
 				if (model_undef) {
-					std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+					std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 					undefGating(y, yy, undef_y);
 				}
 				log_assert(!model_undef || arith_undef_handled);
@@ -599,9 +599,9 @@ struct SatGen
 
 		if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 
 			int extend_bit = ez->FALSE;
 
@@ -632,9 +632,9 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				std::vector<int> undef_a_shifted;
 
 				if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool())
@@ -670,9 +670,9 @@ struct SatGen
 
 		if (cell->type == "$mul")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -689,7 +689,7 @@ struct SatGen
 
 			if (model_undef) {
 				log_assert(arith_undef_handled);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -697,9 +697,9 @@ struct SatGen
 
 		if (cell->type == "$div" || cell->type == "$mod")
 		{
-			std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -753,11 +753,11 @@ struct SatGen
 						only_first_one.at(0) = ez->TRUE;
 						div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
 					} else {
-						div_zero_result.insert(div_zero_result.end(), cell->get("\\A").size(), ez->TRUE);
+						div_zero_result.insert(div_zero_result.end(), cell->getPort("\\A").size(), ez->TRUE);
 						div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
 					}
 				} else {
-					int copy_a_bits = std::min(cell->get("\\A").size(), cell->get("\\B").size());
+					int copy_a_bits = std::min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
 					div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
 					if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
 						div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
@@ -769,7 +769,7 @@ struct SatGen
 
 			if (model_undef) {
 				log_assert(arith_undef_handled);
-				std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -777,17 +777,17 @@ struct SatGen
 
 		if (cell->type == "$slice")
 		{
-			RTLIL::SigSpec a = cell->get("\\A");
-			RTLIL::SigSpec y = cell->get("\\Y");
+			RTLIL::SigSpec a = cell->getPort("\\A");
+			RTLIL::SigSpec y = cell->getPort("\\Y");
 			ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep));
 			return true;
 		}
 
 		if (cell->type == "$concat")
 		{
-			RTLIL::SigSpec a = cell->get("\\A");
-			RTLIL::SigSpec b = cell->get("\\B");
-			RTLIL::SigSpec y = cell->get("\\Y");
+			RTLIL::SigSpec a = cell->getPort("\\A");
+			RTLIL::SigSpec b = cell->getPort("\\B");
+			RTLIL::SigSpec y = cell->getPort("\\Y");
 
 			RTLIL::SigSpec ab = a;
 			ab.append(b);
@@ -800,20 +800,20 @@ struct SatGen
 		{
 			if (timestep == 1)
 			{
-				initial_state.add((*sigmap)(cell->get("\\Q")));
+				initial_state.add((*sigmap)(cell->getPort("\\Q")));
 			}
 			else
 			{
-				std::vector<int> d = importDefSigSpec(cell->get("\\D"), timestep-1);
-				std::vector<int> q = importDefSigSpec(cell->get("\\Q"), timestep);
+				std::vector<int> d = importDefSigSpec(cell->getPort("\\D"), timestep-1);
+				std::vector<int> q = importDefSigSpec(cell->getPort("\\Q"), timestep);
 
 				std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
 				ez->assume(ez->vec_eq(d, qq));
 
 				if (model_undef)
 				{
-					std::vector<int> undef_d = importUndefSigSpec(cell->get("\\D"), timestep-1);
-					std::vector<int> undef_q = importUndefSigSpec(cell->get("\\Q"), timestep);
+					std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1);
+					std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep);
 
 					ez->assume(ez->vec_eq(undef_d, undef_q));
 					undefGating(q, qq, undef_q);
@@ -825,8 +825,8 @@ struct SatGen
 		if (cell->type == "$assert")
 		{
 			std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
-			asserts_a[pf].append((*sigmap)(cell->get("\\A")));
-			asserts_en[pf].append((*sigmap)(cell->get("\\EN")));
+			asserts_a[pf].append((*sigmap)(cell->getPort("\\A")));
+			asserts_en[pf].append((*sigmap)(cell->getPort("\\EN")));
 			return true;
 		}
 
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index d204e93c6..4b2e82ca7 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -110,11 +110,11 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 	{
 		if (clk_polarity != (cell->type == "$_DFF_P_"))
 			return;
-		if (clk_sig != assign_map(cell->get("\\C")))
+		if (clk_sig != assign_map(cell->getPort("\\C")))
 			return;
 
-		RTLIL::SigSpec sig_d = cell->get("\\D");
-		RTLIL::SigSpec sig_q = cell->get("\\Q");
+		RTLIL::SigSpec sig_d = cell->getPort("\\D");
+		RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 
 		if (keepff)
 			for (auto &c : sig_q.chunks())
@@ -132,8 +132,8 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 	if (cell->type == "$_INV_")
 	{
-		RTLIL::SigSpec sig_a = cell->get("\\A");
-		RTLIL::SigSpec sig_y = cell->get("\\Y");
+		RTLIL::SigSpec sig_a = cell->getPort("\\A");
+		RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 		assign_map.apply(sig_a);
 		assign_map.apply(sig_y);
@@ -146,9 +146,9 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 	if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_")
 	{
-		RTLIL::SigSpec sig_a = cell->get("\\A");
-		RTLIL::SigSpec sig_b = cell->get("\\B");
-		RTLIL::SigSpec sig_y = cell->get("\\Y");
+		RTLIL::SigSpec sig_a = cell->getPort("\\A");
+		RTLIL::SigSpec sig_b = cell->getPort("\\B");
+		RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 		assign_map.apply(sig_a);
 		assign_map.apply(sig_b);
@@ -172,10 +172,10 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 	if (cell->type == "$_MUX_")
 	{
-		RTLIL::SigSpec sig_a = cell->get("\\A");
-		RTLIL::SigSpec sig_b = cell->get("\\B");
-		RTLIL::SigSpec sig_s = cell->get("\\S");
-		RTLIL::SigSpec sig_y = cell->get("\\Y");
+		RTLIL::SigSpec sig_a = cell->getPort("\\A");
+		RTLIL::SigSpec sig_b = cell->getPort("\\B");
+		RTLIL::SigSpec sig_s = cell->getPort("\\S");
+		RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 		assign_map.apply(sig_a);
 		assign_map.apply(sig_b);
@@ -467,7 +467,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 			if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_")
 				continue;
 
-			std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->get("\\C")));
+			std::pair<bool, RTLIL::SigSpec> key(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")));
 			if (++dff_counters[key] > best_dff_counter) {
 				best_dff_counter = dff_counters[key];
 				clk_polarity = key.first;
@@ -700,48 +700,48 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 				cell_stats[RTLIL::unescape_id(c->type)]++;
 				if (c->type == "\\ZERO" || c->type == "\\ONE") {
 					RTLIL::SigSig conn;
-					conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]);
+					conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
 					conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
 					module->connect(conn);
 					continue;
 				}
 				if (c->type == "\\BUF") {
 					RTLIL::SigSig conn;
-					conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]);
-					conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]);
+					conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
+					conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]);
 					module->connect(conn);
 					continue;
 				}
 				if (c->type == "\\INV") {
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_");
-					cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]));
-					cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]));
+					cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
+					cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
 					design->select(module, cell);
 					continue;
 				}
 				if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") {
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
-					cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]));
-					cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)]));
-					cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]));
+					cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
+					cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
+					cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
 					design->select(module, cell);
 					continue;
 				}
 				if (c->type == "\\MUX") {
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
-					cell->set("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\A").as_wire()->name)]));
-					cell->set("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\B").as_wire()->name)]));
-					cell->set("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\S").as_wire()->name)]));
-					cell->set("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Y").as_wire()->name)]));
+					cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
+					cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
+					cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
+					cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
 					design->select(module, cell);
 					continue;
 				}
 				if (c->type == "\\DFF") {
 					log_assert(clk_sig.size() == 1);
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
-					cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)]));
-					cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)]));
-					cell->set("\\C", clk_sig);
+					cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
+					cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
+					cell->setPort("\\C", clk_sig);
 					design->select(module, cell);
 					continue;
 				}
@@ -764,9 +764,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 				if (c->type == "\\_dff_") {
 					log_assert(clk_sig.size() == 1);
 					RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
-					cell->set("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\D").as_wire()->name)]));
-					cell->set("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->get("\\Q").as_wire()->name)]));
-					cell->set("\\C", clk_sig);
+					cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
+					cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
+					cell->setPort("\\C", clk_sig);
 					design->select(module, cell);
 					continue;
 				}
@@ -780,7 +780,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 						log_assert(c.width == 1);
 						newsig.append(module->wires_[remap_name(c.wire->name)]);
 					}
-					cell->set(conn.first, newsig);
+					cell->setPort(conn.first, newsig);
 				}
 				design->select(module, cell);
 			}
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index e10cb109f..1891a7450 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -120,8 +120,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 					module->addWire(RTLIL::escape_id(q));
 
 				RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
-				cell->set("\\D", module->wires_.at(RTLIL::escape_id(d)));
-				cell->set("\\Q", module->wires_.at(RTLIL::escape_id(q)));
+				cell->setPort("\\D", module->wires_.at(RTLIL::escape_id(d)));
+				cell->setPort("\\Q", module->wires_.at(RTLIL::escape_id(q)));
 				continue;
 			}
 
@@ -140,7 +140,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 					*(q++) = 0;
 					if (module->wires_.count(RTLIL::escape_id(q)) == 0)
 						module->addWire(RTLIL::escape_id(q));
-					cell->set(RTLIL::escape_id(p), module->wires_.at(RTLIL::escape_id(q)));
+					cell->setPort(RTLIL::escape_id(p), module->wires_.at(RTLIL::escape_id(q)));
 				}
 				continue;
 			}
@@ -196,8 +196,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 				RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
 				cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
 				cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
-				cell->set("\\I", input_sig);
-				cell->set("\\O", output_sig);
+				cell->setPort("\\I", input_sig);
+				cell->setPort("\\O", output_sig);
 				lutptr = &cell->parameters.at("\\LUT");
 				lut_default_state = RTLIL::State::Sx;
 				continue;
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 62995a49d..e3fde8559 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -72,10 +72,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 			continue;
 		if (mod->get_bool_attribute("\\blackbox"))
 			continue;
-		if (it.second->has(name))
+		if (it.second->hasPort(name))
 			continue;
 
-		it.second->set(name, wire);
+		it.second->setPort(name, wire);
 		log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
 	}
 }
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index 3e13fd4d4..30c80f732 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -176,7 +176,7 @@ struct ConnectPass : public Pass {
 			if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
 				log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
 
-			module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
+			module->cells_.at(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig));
 		}
 		else
 			log_cmd_error("Expected -set, -unset, or -port.\n");
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 5fce2d6cb..07c6150cc 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -74,9 +74,9 @@ struct SpliceWorker
 			cell->parameters["\\OFFSET"] = offset;
 			cell->parameters["\\A_WIDTH"] = sig_a.size();
 			cell->parameters["\\Y_WIDTH"] = sig.size();
-			cell->set("\\A", sig_a);
-			cell->set("\\Y", module->addWire(NEW_ID, sig.size()));
-			new_sig = cell->get("\\Y");
+			cell->setPort("\\A", sig_a);
+			cell->setPort("\\Y", module->addWire(NEW_ID, sig.size()));
+			new_sig = cell->getPort("\\Y");
 		}
 
 		sliced_signals_cache[sig] = new_sig;
@@ -130,10 +130,10 @@ struct SpliceWorker
 			RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
 			cell->parameters["\\A_WIDTH"] = new_sig.size();
 			cell->parameters["\\B_WIDTH"] = sig2.size();
-			cell->set("\\A", new_sig);
-			cell->set("\\B", sig2);
-			cell->set("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
-			new_sig = cell->get("\\Y");
+			cell->setPort("\\A", new_sig);
+			cell->setPort("\\B", sig2);
+			cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
+			new_sig = cell->getPort("\\Y");
 		}
 
 		spliced_signals_cache[sig] = new_sig;
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index a619cf57d..6025de15b 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -52,8 +52,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
 	for (auto &cellport : cellport_list) {
 		if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
 			return false;
-		RTLIL::SigSpec sig_a = assign_map(cellport.first->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cellport.first->get("\\B"));
+		RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
 		if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
 			return false;
 		for (int i = 0; i < sig_b.size(); i += sig_a.size())
@@ -80,14 +80,14 @@ static bool check_state_users(RTLIL::SigSpec sig)
 			continue;
 		if (cellport.second != "\\A" && cellport.second != "\\B")
 			return false;
-		if (!cell->has("\\A") || !cell->has("\\B") || !cell->has("\\Y"))
+		if (!cell->hasPort("\\A") || !cell->hasPort("\\B") || !cell->hasPort("\\Y"))
 			return false;
 		for (auto &port_it : cell->connections())
 			if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y")
 				return false;
-		if (assign_map(cell->get("\\A")) == sig && cell->get("\\B").is_fully_const())
+		if (assign_map(cell->getPort("\\A")) == sig && cell->getPort("\\B").is_fully_const())
 			continue;
-		if (assign_map(cell->get("\\B")) == sig && cell->get("\\A").is_fully_const())
+		if (assign_map(cell->getPort("\\B")) == sig && cell->getPort("\\A").is_fully_const())
 			continue;
 		return false;
 	}
@@ -109,8 +109,8 @@ static void detect_fsm(RTLIL::Wire *wire)
 			continue;
 		muxtree_cells.clear();
 		SigPool recursion_monitor;
-		RTLIL::SigSpec sig_q = assign_map(cellport.first->get("\\Q"));
-		RTLIL::SigSpec sig_d = assign_map(cellport.first->get("\\D"));
+		RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q"));
+		RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D"));
 		if (sig_q == RTLIL::SigSpec(wire) && check_state_mux_tree(sig_q, sig_d, recursion_monitor) && check_state_users(sig_q)) {
 			log("Found FSM state register %s in module %s.\n", wire->name.c_str(), module->name.c_str());
 			wire->attributes["\\fsm_encoding"] = RTLIL::Const("auto");
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 2da4794eb..670fae1d9 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -43,34 +43,34 @@ struct FsmExpand
 	bool is_cell_merge_candidate(RTLIL::Cell *cell)
 	{
 		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
-			if (cell->get("\\A").size() < 2)
+			if (cell->getPort("\\A").size() < 2)
 				return true;
 
 		RTLIL::SigSpec new_signals;
-		if (cell->has("\\A"))
-			new_signals.append(assign_map(cell->get("\\A")));
-		if (cell->has("\\B"))
-			new_signals.append(assign_map(cell->get("\\B")));
-		if (cell->has("\\S"))
-			new_signals.append(assign_map(cell->get("\\S")));
-		if (cell->has("\\Y"))
-			new_signals.append(assign_map(cell->get("\\Y")));
+		if (cell->hasPort("\\A"))
+			new_signals.append(assign_map(cell->getPort("\\A")));
+		if (cell->hasPort("\\B"))
+			new_signals.append(assign_map(cell->getPort("\\B")));
+		if (cell->hasPort("\\S"))
+			new_signals.append(assign_map(cell->getPort("\\S")));
+		if (cell->hasPort("\\Y"))
+			new_signals.append(assign_map(cell->getPort("\\Y")));
 
 		new_signals.sort_and_unify();
 		new_signals.remove_const();
 
-		new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN")));
-		new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT")));
+		new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
+		new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
 
 		if (new_signals.size() > 3)
 			return false;
 
-		if (cell->has("\\Y")) {
-			new_signals.append(assign_map(cell->get("\\Y")));
+		if (cell->hasPort("\\Y")) {
+			new_signals.append(assign_map(cell->getPort("\\Y")));
 			new_signals.sort_and_unify();
 			new_signals.remove_const();
-			new_signals.remove(assign_map(fsm_cell->get("\\CTRL_IN")));
-			new_signals.remove(assign_map(fsm_cell->get("\\CTRL_OUT")));
+			new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
+			new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
 		}
 
 		if (new_signals.size() > 2)
@@ -83,10 +83,10 @@ struct FsmExpand
 	{
 		std::vector<RTLIL::Cell*> cell_list;
 
-		for (auto c : sig2driver.find(assign_map(fsm_cell->get("\\CTRL_IN"))))
+		for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN"))))
 			cell_list.push_back(c);
 
-		for (auto c : sig2user.find(assign_map(fsm_cell->get("\\CTRL_OUT"))))
+		for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT"))))
 			cell_list.push_back(c);
 
 		current_set.clear();
@@ -148,12 +148,12 @@ struct FsmExpand
 		for (int i = 0; i < (1 << input_sig.size()); i++) {
 			RTLIL::Const in_val(i, input_sig.size());
 			RTLIL::SigSpec A, B, S;
-			if (cell->has("\\A"))
-				A = assign_map(cell->get("\\A"));
-			if (cell->has("\\B"))
-				B = assign_map(cell->get("\\B"));
-			if (cell->has("\\S"))
-				S = assign_map(cell->get("\\S"));
+			if (cell->hasPort("\\A"))
+				A = assign_map(cell->getPort("\\A"));
+			if (cell->hasPort("\\B"))
+				B = assign_map(cell->getPort("\\B"));
+			if (cell->hasPort("\\S"))
+				S = assign_map(cell->getPort("\\S"));
 			A.replace(input_sig, RTLIL::SigSpec(in_val));
 			B.replace(input_sig, RTLIL::SigSpec(in_val));
 			S.replace(input_sig, RTLIL::SigSpec(in_val));
@@ -167,14 +167,14 @@ struct FsmExpand
 		fsm_data.copy_from_cell(fsm_cell);
 
 		fsm_data.num_inputs += input_sig.size();
-		RTLIL::SigSpec new_ctrl_in = fsm_cell->get("\\CTRL_IN");
+		RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN");
 		new_ctrl_in.append(input_sig);
-		fsm_cell->set("\\CTRL_IN", new_ctrl_in);
+		fsm_cell->setPort("\\CTRL_IN", new_ctrl_in);
 
 		fsm_data.num_outputs += output_sig.size();
-		RTLIL::SigSpec new_ctrl_out = fsm_cell->get("\\CTRL_OUT");
+		RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
 		new_ctrl_out.append(output_sig);
-		fsm_cell->set("\\CTRL_OUT", new_ctrl_out);
+		fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out);
 
 		std::vector<FsmData::transition_t> new_transition_table;
 		for (auto &tr : fsm_data.transition_table) {
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 718f779b6..cf2075fba 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -58,9 +58,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 			log("  unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
 			return false;
 		}
-		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));
+		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+		RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
 		if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef())
 			do {
 				if (sig_a.is_fully_def())
@@ -183,12 +183,12 @@ static void extract_fsm(RTLIL::Wire *wire)
 		if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
 			continue;
 		log("  found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
-		RTLIL::SigSpec sig_q = assign_map(cell->get("\\Q"));
-		RTLIL::SigSpec sig_d = assign_map(cell->get("\\D"));
-		clk = cell->get("\\CLK");
+		RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q"));
+		RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D"));
+		clk = cell->getPort("\\CLK");
 		clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 		if (cell->type == "$adff") {
-			arst = cell->get("\\ARST");
+			arst = cell->getPort("\\ARST");
 			arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
 			reset_state = cell->parameters["\\ARST_VALUE"];
 		}
@@ -224,9 +224,9 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2trigger.find(dff_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells_.at(cellport.first);
-		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
+		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+		RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
 		if (cellport.second == "\\A" && !sig_b.is_fully_const())
 			continue;
 		if (cellport.second == "\\B" && !sig_a.is_fully_const())
@@ -271,12 +271,12 @@ static void extract_fsm(RTLIL::Wire *wire)
 	// create fsm cell
 
 	RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
-	fsm_cell->set("\\CLK", clk);
-	fsm_cell->set("\\ARST", arst);
+	fsm_cell->setPort("\\CLK", clk);
+	fsm_cell->setPort("\\ARST", arst);
 	fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1);
 	fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1);
-	fsm_cell->set("\\CTRL_IN", ctrl_in);
-	fsm_cell->set("\\CTRL_OUT", ctrl_out);
+	fsm_cell->setPort("\\CTRL_IN", ctrl_in);
+	fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
 	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
 	fsm_cell->attributes = wire->attributes;
 	fsm_data.copy_to_cell(fsm_cell);
@@ -294,7 +294,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2driver.find(ctrl_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells_.at(cellport.first);
-		RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
+		RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
 		RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size());
 		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
@@ -347,8 +347,8 @@ struct FsmExtractPass : public Pass {
 						assign_map.apply(sig);
 						sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
 					}
-					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->has("\\Y") &&
-							cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
+					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->hasPort("\\Y") &&
+							cell_it.second->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 8b9ad6be7..99b736c1b 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -58,9 +58,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 			and_sig.append(RTLIL::SigSpec(eq_wire));
 
 			RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
-			eq_cell->set("\\A", eq_sig_a);
-			eq_cell->set("\\B", eq_sig_b);
-			eq_cell->set("\\Y", RTLIL::SigSpec(eq_wire));
+			eq_cell->setPort("\\A", eq_sig_a);
+			eq_cell->setPort("\\B", eq_sig_b);
+			eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire));
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
@@ -80,8 +80,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				and_sig.append(RTLIL::SigSpec(or_wire));
 
 				RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
-				or_cell->set("\\A", or_sig);
-				or_cell->set("\\Y", RTLIL::SigSpec(or_wire));
+				or_cell->setPort("\\A", or_sig);
+				or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire));
 				or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 				or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
 				or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@@ -96,9 +96,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 				cases_vector.append(RTLIL::SigSpec(and_wire));
 
 				RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
-				and_cell->set("\\A", and_sig.extract(0, 1));
-				and_cell->set("\\B", and_sig.extract(1, 1));
-				and_cell->set("\\Y", RTLIL::SigSpec(and_wire));
+				and_cell->setPort("\\A", and_sig.extract(0, 1));
+				and_cell->setPort("\\B", and_sig.extract(1, 1));
+				and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire));
 				and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 				and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 				and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
@@ -119,8 +119,8 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 
 	if (cases_vector.size() > 1) {
 		RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
-		or_cell->set("\\A", cases_vector);
-		or_cell->set("\\Y", output);
+		or_cell->setPort("\\A", cases_vector);
+		or_cell->setPort("\\Y", output);
 		or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 		or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
 		or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
@@ -138,8 +138,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	FsmData fsm_data;
 	fsm_data.copy_from_cell(fsm_cell);
 
-	RTLIL::SigSpec ctrl_in = fsm_cell->get("\\CTRL_IN");
-	RTLIL::SigSpec ctrl_out = fsm_cell->get("\\CTRL_OUT");
+	RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN");
+	RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
 
 	// create state register
 
@@ -151,7 +151,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
 
 	RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
-	if (fsm_cell->get("\\ARST").is_fully_const()) {
+	if (fsm_cell->getPort("\\ARST").is_fully_const()) {
 		state_dff->type = "$dff";
 	} else {
 		state_dff->type = "$adff";
@@ -160,13 +160,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
 			if (bit != RTLIL::State::S1)
 				bit = RTLIL::State::S0;
-		state_dff->set("\\ARST", fsm_cell->get("\\ARST"));
+		state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST"));
 	}
 	state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
 	state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
-	state_dff->set("\\CLK", fsm_cell->get("\\CLK"));
-	state_dff->set("\\D", RTLIL::SigSpec(next_state_wire));
-	state_dff->set("\\Q", RTLIL::SigSpec(state_wire));
+	state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK"));
+	state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire));
+	state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire));
 
 	// decode state register
 
@@ -194,9 +194,9 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 			encoding_is_onehot = false;
 
 			RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
-			eq_cell->set("\\A", sig_a);
-			eq_cell->set("\\B", sig_b);
-			eq_cell->set("\\Y", RTLIL::SigSpec(state_onehot, i));
+			eq_cell->setPort("\\A", sig_a);
+			eq_cell->setPort("\\B", sig_b);
+			eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i));
 			eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
 			eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@@ -260,10 +260,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		}
 
 		RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux");
-		mux_cell->set("\\A", sig_a);
-		mux_cell->set("\\B", sig_b);
-		mux_cell->set("\\S", sig_s);
-		mux_cell->set("\\Y", RTLIL::SigSpec(next_state_wire));
+		mux_cell->setPort("\\A", sig_a);
+		mux_cell->setPort("\\B", sig_b);
+		mux_cell->setPort("\\S", sig_s);
+		mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
 		mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
 		mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
 	}
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 9d9156ae3..bcaa89bf0 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -52,7 +52,7 @@ struct FsmOpt
 
 	void opt_const_and_unused_inputs()
 	{
-		RTLIL::SigSpec ctrl_in = cell->get("\\CTRL_IN");
+		RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN");
 		std::vector<bool> ctrl_in_used(ctrl_in.size());
 
 		std::vector<FsmData::transition_t> new_transition_table;
@@ -73,15 +73,15 @@ struct FsmOpt
 
 		for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
 			if (!ctrl_in_used[i]) {
-				log("  Removing unused input signal %s.\n", log_signal(cell->get("\\CTRL_IN").extract(i, 1)));
+				log("  Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1)));
 				for (auto &tr : new_transition_table) {
 					RTLIL::SigSpec tmp(tr.ctrl_in);
 					tmp.remove(i, 1);
 					tr.ctrl_in = tmp.as_const();
 				}
-				RTLIL::SigSpec new_ctrl_in = cell->get("\\CTRL_IN");
+				RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN");
 				new_ctrl_in.remove(i, 1);
-				cell->set("\\CTRL_IN", new_ctrl_in);
+				cell->setPort("\\CTRL_IN", new_ctrl_in);
 				fsm_data.num_inputs--;
 			}
 		}
@@ -93,12 +93,12 @@ struct FsmOpt
 	void opt_unused_outputs()
 	{
 		for (int i = 0; i < fsm_data.num_outputs; i++) {
-			RTLIL::SigSpec sig = cell->get("\\CTRL_OUT").extract(i, 1);
+			RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1);
 			if (signal_is_unused(sig)) {
 				log("  Removing unused output signal %s.\n", log_signal(sig));
-				RTLIL::SigSpec new_ctrl_out = cell->get("\\CTRL_OUT");
+				RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT");
 				new_ctrl_out.remove(i, 1);
-				cell->set("\\CTRL_OUT", new_ctrl_out);
+				cell->setPort("\\CTRL_OUT", new_ctrl_out);
 				for (auto &tr : fsm_data.transition_table) {
 					RTLIL::SigSpec tmp(tr.ctrl_out);
 					tmp.remove(i, 1);
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 8f0e5d621..7a44dd452 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -141,13 +141,13 @@ struct FsmData
 
 		log("\n");
 		log("  Input signals:\n");
-		RTLIL::SigSpec sig_in = cell->get("\\CTRL_IN");
+		RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
 		for (int i = 0; i < SIZE(sig_in); i++)
 			log("  %3d: %s\n", i, log_signal(sig_in[i]));
 
 		log("\n");
 		log("  Output signals:\n");
-		RTLIL::SigSpec sig_out = cell->get("\\CTRL_OUT");
+		RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
 		for (int i = 0; i < SIZE(sig_out); i++)
 			log("  %3d: %s\n", i, log_signal(sig_out[i]));
 
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index d0c9f4b5a..2a47002ef 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -185,7 +185,7 @@ struct SubmodWorker
 			RTLIL::Wire *old_wire = it.first;
 			RTLIL::Wire *new_wire = it.second.new_wire;
 			if (new_wire->port_id > 0)
-				new_cell->set(new_wire->name, RTLIL::SigSpec(old_wire));
+				new_cell->setPort(new_wire->name, RTLIL::SigSpec(old_wire));
 		}
 	}
 
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index aecb7bd6c..8887d1952 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -75,12 +75,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 			wr_ports++;
 			del_cells.push_back(cell);
 
-			RTLIL::SigSpec clk = cell->get("\\CLK");
+			RTLIL::SigSpec clk = cell->getPort("\\CLK");
 			RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
 			RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
-			RTLIL::SigSpec addr = cell->get("\\ADDR");
-			RTLIL::SigSpec data = cell->get("\\DATA");
-			RTLIL::SigSpec en = cell->get("\\EN");
+			RTLIL::SigSpec addr = cell->getPort("\\ADDR");
+			RTLIL::SigSpec data = cell->getPort("\\DATA");
+			RTLIL::SigSpec en = cell->getPort("\\EN");
 
 			clk.extend(1, false);
 			clk_enable.extend(1, false);
@@ -102,12 +102,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 			rd_ports++;
 			del_cells.push_back(cell);
 
-			RTLIL::SigSpec clk = cell->get("\\CLK");
+			RTLIL::SigSpec clk = cell->getPort("\\CLK");
 			RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
 			RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
 			RTLIL::SigSpec transparent = RTLIL::SigSpec(cell->parameters["\\TRANSPARENT"]);
-			RTLIL::SigSpec addr = cell->get("\\ADDR");
-			RTLIL::SigSpec data = cell->get("\\DATA");
+			RTLIL::SigSpec addr = cell->getPort("\\ADDR");
+			RTLIL::SigSpec data = cell->getPort("\\DATA");
 
 			clk.extend(1, false);
 			clk_enable.extend(1, false);
@@ -146,10 +146,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
 	mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0);
 
-	mem->set("\\WR_CLK", sig_wr_clk);
-	mem->set("\\WR_ADDR", sig_wr_addr);
-	mem->set("\\WR_DATA", sig_wr_data);
-	mem->set("\\WR_EN", sig_wr_en);
+	mem->setPort("\\WR_CLK", sig_wr_clk);
+	mem->setPort("\\WR_ADDR", sig_wr_addr);
+	mem->setPort("\\WR_DATA", sig_wr_data);
+	mem->setPort("\\WR_EN", sig_wr_en);
 
 	log_assert(sig_rd_clk.size() == rd_ports);
 	log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
@@ -162,9 +162,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0);
 	mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0);
 
-	mem->set("\\RD_CLK", sig_rd_clk);
-	mem->set("\\RD_ADDR", sig_rd_addr);
-	mem->set("\\RD_DATA", sig_rd_data);
+	mem->setPort("\\RD_CLK", sig_rd_clk);
+	mem->setPort("\\RD_ADDR", sig_rd_addr);
+	mem->setPort("\\RD_DATA", sig_rd_data);
 
 	for (auto c : del_cells)
 		module->remove(c);
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 6cbce781f..e92d726cc 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -43,21 +43,21 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
 				continue;
 
 			if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-				if (cell->get("\\CLK") != clk)
+				if (cell->getPort("\\CLK") != clk)
 					continue;
 				if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
 					continue;
 			}
 
-			RTLIL::SigSpec q_norm = cell->get(after ? "\\D" : "\\Q");
+			RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
 			normalize_sig(module, q_norm);
 
-			RTLIL::SigSpec d = q_norm.extract(bit, &cell->get(after ? "\\Q" : "\\D"));
+			RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
 			if (d.size() != 1)
 				continue;
 
 			bit = d;
-			clk = cell->get("\\CLK");
+			clk = cell->getPort("\\CLK");
 			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 			goto replaced_this_bit;
 		}
@@ -76,29 +76,29 @@ static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
 	bool clk_polarity = 0;
 
-	RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
+	RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
 	if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
 		log("no (compatible) $dff for address input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_data = cell->get("\\DATA");
+	RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
 	if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
 		log("no (compatible) $dff for data input found.\n");
 		return;
 	}
 
-	RTLIL::SigSpec sig_en = cell->get("\\EN");
+	RTLIL::SigSpec sig_en = cell->getPort("\\EN");
 	if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
 		log("no (compatible) $dff for enable input found.\n");
 		return;
 	}
 
 	if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-		cell->set("\\CLK", clk);
-		cell->set("\\ADDR", sig_addr);
-		cell->set("\\DATA", sig_data);
-		cell->set("\\EN", sig_en);
+		cell->setPort("\\CLK", clk);
+		cell->setPort("\\ADDR", sig_addr);
+		cell->setPort("\\DATA", sig_data);
+		cell->setPort("\\EN", sig_en);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		log("merged $dff to cell.\n");
@@ -119,9 +119,9 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
 
 	for (auto cell : module->cells())
 		if (cell->type == "$dff") {
-			RTLIL::SigSpec new_q = cell->get("\\Q");
+			RTLIL::SigSpec new_q = cell->getPort("\\Q");
 			new_q.replace(sig, new_sig);
-			cell->set("\\Q", new_q);
+			cell->setPort("\\Q", new_q);
 		}
 }
 
@@ -132,13 +132,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	bool clk_polarity = 0;
 
 	RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_data = cell->get("\\DATA");
+	RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
 	if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true) &&
 			clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
 		disconnect_dff(module, sig_data);
-		cell->set("\\CLK", clk_data);
-		cell->set("\\DATA", sig_data);
+		cell->setPort("\\CLK", clk_data);
+		cell->setPort("\\DATA", sig_data);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
@@ -147,12 +147,12 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_addr = cell->get("\\ADDR");
+	RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
 	if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity) &&
 			clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
 	{
-		cell->set("\\CLK", clk_addr);
-		cell->set("\\ADDR", sig_addr);
+		cell->setPort("\\CLK", clk_addr);
+		cell->setPort("\\ADDR", sig_addr);
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
 		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 0000bd507..f1917b972 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -61,20 +61,20 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	// all write ports must share the same clock
-	RTLIL::SigSpec clocks = cell->get("\\WR_CLK");
+	RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
 	RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
 	RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
 	RTLIL::SigSpec refclock;
 	RTLIL::State refclock_pol = RTLIL::State::Sx;
 	for (int i = 0; i < clocks.size(); i++) {
-		RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(i * mem_width, mem_width);
+		RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width);
 		if (wr_en.is_fully_const() && !wr_en.as_bool()) {
 			static_ports.insert(i);
 			continue;
 		}
 		if (clocks_en.bits[i] != RTLIL::State::S1) {
-			RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(i*mem_abits, mem_abits);
-			RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(i*mem_width, mem_width);
+			RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits);
+			RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width);
 			if (wr_addr.is_fully_const()) {
 				// FIXME: Actually we should check for wr_en.is_fully_const() also and
 				// create a $adff cell with this ports wr_en input as reset pin when wr_en
@@ -119,15 +119,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
 			if (clocks_pol.bits.size() > 0) {
 				c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
-				c->set("\\CLK", clocks.extract(0, 1));
+				c->setPort("\\CLK", clocks.extract(0, 1));
 			} else {
 				c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
-				c->set("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
+				c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
 			}
 
 			RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
 			data_reg_in.push_back(RTLIL::SigSpec(w_in));
-			c->set("\\D", data_reg_in.back());
+			c->setPort("\\D", data_reg_in.back());
 
 			std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
 			if (module->wires_.count(w_out_name) > 0)
@@ -137,7 +137,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			w_out->start_offset = mem_offset;
 
 			data_reg_out.push_back(RTLIL::SigSpec(w_out));
-			c->set("\\Q", data_reg_out.back());
+			c->setPort("\\Q", data_reg_out.back());
 		}
 	}
 
@@ -147,10 +147,10 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
 	{
-		RTLIL::SigSpec rd_addr = cell->get("\\RD_ADDR").extract(i*mem_abits, mem_abits);
+		RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits);
 
 		std::vector<RTLIL::SigSpec> rd_signals;
-		rd_signals.push_back(cell->get("\\RD_DATA").extract(i*mem_width, mem_width));
+		rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width));
 
 		if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
 		{
@@ -159,13 +159,13 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 				RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
 				c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
 				c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
-				c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1));
-				c->set("\\D", rd_addr);
+				c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
+				c->setPort("\\D", rd_addr);
 				count_dff++;
 
 				RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
 
-				c->set("\\Q", RTLIL::SigSpec(w));
+				c->setPort("\\Q", RTLIL::SigSpec(w));
 				rd_addr = RTLIL::SigSpec(w);
 			}
 			else
@@ -173,15 +173,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 				RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
 				c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
 				c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
-				c->set("\\CLK", cell->get("\\RD_CLK").extract(i, 1));
-				c->set("\\Q", rd_signals.back());
+				c->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
+				c->setPort("\\Q", rd_signals.back());
 				count_dff++;
 
 				RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
 
 				rd_signals.clear();
 				rd_signals.push_back(RTLIL::SigSpec(w));
-				c->set("\\D", rd_signals.back());
+				c->setPort("\\D", rd_signals.back());
 			}
 		}
 
@@ -193,15 +193,15 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			{
 				RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
 				c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
-				c->set("\\Y", rd_signals[k]);
-				c->set("\\S", rd_addr.extract(mem_abits-j-1, 1));
+				c->setPort("\\Y", rd_signals[k]);
+				c->setPort("\\S", rd_addr.extract(mem_abits-j-1, 1));
 				count_mux++;
 
-				c->set("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
-				c->set("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
+				c->setPort("\\A", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$a"), mem_width));
+				c->setPort("\\B", module->addWire(genid(cell->name, "$rdmux", i, "", j, "", k, "$b"), mem_width));
 
-				next_rd_signals.push_back(c->get("\\A"));
-				next_rd_signals.push_back(c->get("\\B"));
+				next_rd_signals.push_back(c->getPort("\\A"));
+				next_rd_signals.push_back(c->getPort("\\B"));
 			}
 
 			next_rd_signals.swap(rd_signals);
@@ -222,9 +222,9 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 
 		for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
 		{
-			RTLIL::SigSpec wr_addr = cell->get("\\WR_ADDR").extract(j*mem_abits, mem_abits);
-			RTLIL::SigSpec wr_data = cell->get("\\WR_DATA").extract(j*mem_width, mem_width);
-			RTLIL::SigSpec wr_en = cell->get("\\WR_EN").extract(j*mem_width, mem_width);
+			RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits);
+			RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width);
+			RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width);
 
 			RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq");
 			c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
@@ -232,12 +232,12 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"];
 			c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"];
 			c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			c->set("\\A", RTLIL::SigSpec(i, mem_abits));
-			c->set("\\B", wr_addr);
+			c->setPort("\\A", RTLIL::SigSpec(i, mem_abits));
+			c->setPort("\\B", wr_addr);
 			count_wrmux++;
 
 			RTLIL::Wire *w_seladdr = module->addWire(genid(cell->name, "$wreq", i, "", j, "$y"));
-			c->set("\\Y", w_seladdr);
+			c->setPort("\\Y", w_seladdr);
 
 			int wr_offset = 0;
 			while (wr_offset < wr_en.size())
@@ -262,21 +262,21 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 					c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
 					c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
 					c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-					c->set("\\A", w);
-					c->set("\\B", wr_bit);
+					c->setPort("\\A", w);
+					c->setPort("\\B", wr_bit);
 
 					w = module->addWire(genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y"));
-					c->set("\\Y", RTLIL::SigSpec(w));
+					c->setPort("\\Y", RTLIL::SigSpec(w));
 				}
 
 				c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
 				c->parameters["\\WIDTH"] = wr_width;
-				c->set("\\A", sig.extract(wr_offset, wr_width));
-				c->set("\\B", wr_data.extract(wr_offset, wr_width));
-				c->set("\\S", RTLIL::SigSpec(w));
+				c->setPort("\\A", sig.extract(wr_offset, wr_width));
+				c->setPort("\\B", wr_data.extract(wr_offset, wr_width));
+				c->setPort("\\S", RTLIL::SigSpec(w));
 
 				w = module->addWire(genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y"), wr_width);
-				c->set("\\Y", w);
+				c->setPort("\\Y", w);
 
 				sig.replace(wr_offset, w);
 				wr_offset += wr_width;
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index b1629b7c4..b6e7cc835 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -64,18 +64,18 @@ struct MemoryShareWorker
 		RTLIL::Cell *cell = sig_to_mux.at(sig).first;
 		int bit_idx = sig_to_mux.at(sig).second;
 
-		std::vector<RTLIL::SigBit> sig_a = sigmap(cell->get("\\A"));
-		std::vector<RTLIL::SigBit> sig_b = sigmap(cell->get("\\B"));
-		std::vector<RTLIL::SigBit> sig_s = sigmap(cell->get("\\S"));
-		std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
+		std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
+		std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
+		std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S"));
+		std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
 		log_assert(sig_y.at(bit_idx) == sig);
 
 		for (int i = 0; i < int(sig_s.size()); i++)
 			if (state.count(sig_s[i]) && state.at(sig_s[i]) == true) {
 				if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), state, conditions)) {
-					RTLIL::SigSpec new_b = cell->get("\\B");
+					RTLIL::SigSpec new_b = cell->getPort("\\B");
 					new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
-					cell->set("\\B", new_b);
+					cell->setPort("\\B", new_b);
 				}
 				return false;
 			}
@@ -90,9 +90,9 @@ struct MemoryShareWorker
 			new_state[sig_s[i]] = true;
 
 			if (find_data_feedback(async_rd_bits, sig_b.at(bit_idx + i*sig_y.size()), new_state, conditions)) {
-				RTLIL::SigSpec new_b = cell->get("\\B");
+				RTLIL::SigSpec new_b = cell->getPort("\\B");
 				new_b.replace(bit_idx + i*sig_y.size(), RTLIL::State::Sx);
-				cell->set("\\B", new_b);
+				cell->setPort("\\B", new_b);
 			}
 		}
 
@@ -101,9 +101,9 @@ struct MemoryShareWorker
 			new_state[sig_s[i]] = false;
 
 		if (find_data_feedback(async_rd_bits, sig_a.at(bit_idx), new_state, conditions)) {
-			RTLIL::SigSpec new_a = cell->get("\\A");
+			RTLIL::SigSpec new_a = cell->getPort("\\A");
 			new_a.replace(bit_idx, RTLIL::State::Sx);
-			cell->set("\\A", new_a);
+			cell->setPort("\\A", new_a);
 		}
 
 		return false;
@@ -150,10 +150,10 @@ struct MemoryShareWorker
 
 			if (cell->type == "$mux" || cell->type == "$pmux")
 			{
-				std::vector<RTLIL::SigBit> sig_a = sigmap(cell->get("\\A"));
-				std::vector<RTLIL::SigBit> sig_b = sigmap(cell->get("\\B"));
-				std::vector<RTLIL::SigBit> sig_s = sigmap(cell->get("\\S"));
-				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
+				std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
+				std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
+				std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort("\\S"));
+				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
 
 				non_feedback_nets.insert(sig_s.begin(), sig_s.end());
 
@@ -200,8 +200,8 @@ struct MemoryShareWorker
 			if (cell->parameters.at("\\CLK_ENABLE").as_bool())
 				continue;
 
-			RTLIL::SigSpec sig_addr = sigmap(cell->get("\\ADDR"));
-			std::vector<RTLIL::SigBit> sig_data = sigmap(cell->get("\\DATA"));
+			RTLIL::SigSpec sig_addr = sigmap(cell->getPort("\\ADDR"));
+			std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort("\\DATA"));
 
 			for (int i = 0; i < int(sig_data.size()); i++)
 				if (non_feedback_nets.count(sig_data[i]))
@@ -221,14 +221,14 @@ struct MemoryShareWorker
 
 		for (auto cell : wr_ports)
 		{
-			RTLIL::SigSpec sig_addr = sigmap_xmux(cell->get("\\ADDR"));
+			RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort("\\ADDR"));
 			if (!async_rd_bits.count(sig_addr))
 				continue;
 
 			log("  Analyzing write port %s.\n", log_id(cell));
 
-			std::vector<RTLIL::SigBit> cell_data = cell->get("\\DATA");
-			std::vector<RTLIL::SigBit> cell_en = cell->get("\\EN");
+			std::vector<RTLIL::SigBit> cell_data = cell->getPort("\\DATA");
+			std::vector<RTLIL::SigBit> cell_en = cell->getPort("\\EN");
 
 			int created_conditions = 0;
 			for (int i = 0; i < int(cell_data.size()); i++)
@@ -248,7 +248,7 @@ struct MemoryShareWorker
 
 			if (created_conditions) {
 				log("    Added enable logic for %d different cases.\n", created_conditions);
-				cell->set("\\EN", cell_en);
+				cell->setPort("\\EN", cell_en);
 			}
 		}
 	}
@@ -366,15 +366,15 @@ struct MemoryShareWorker
 		for (int i = 0; i < int(wr_ports.size()); i++)
 		{
 			RTLIL::Cell *cell = wr_ports.at(i);
-			RTLIL::SigSpec addr = sigmap_xmux(cell->get("\\ADDR"));
+			RTLIL::SigSpec addr = sigmap_xmux(cell->getPort("\\ADDR"));
 
 			if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
-					(cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk ||
+					(cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk ||
 					cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
 			{
 				cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
 				cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
-				cache_clk = sigmap(cell->get("\\CLK"));
+				cache_clk = sigmap(cell->getPort("\\CLK"));
 				last_port_by_addr.clear();
 
 				if (cache_clk_enable)
@@ -386,7 +386,7 @@ struct MemoryShareWorker
 			log("    Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
 
 			log("      Active bits: ");
-			std::vector<RTLIL::SigBit> en_bits = sigmap(cell->get("\\EN"));
+			std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN"));
 			active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
 			for (int k = int(en_bits.size())-1; k >= 0; k--) {
 				active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
@@ -408,13 +408,13 @@ struct MemoryShareWorker
 
 				// Force this ports addr input to addr directly (skip don't care muxes)
 
-				cell->set("\\ADDR", addr);
+				cell->setPort("\\ADDR", addr);
 
 				// If any of the ports between `last_i' and `i' write to the same address, this
 				// will have priority over whatever `last_i` wrote. So we need to revisit those
 				// ports and mask the EN bits accordingly.
 
-				RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->get("\\EN"));
+				RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort("\\EN"));
 
 				for (int j = last_i+1; j < i; j++)
 				{
@@ -429,20 +429,20 @@ struct MemoryShareWorker
 				found_overlapping_bits_i_j:
 						log("      Creating collosion-detect logic for port %d.\n", j);
 						RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
-						module->addEq(NEW_ID, addr, wr_ports[j]->get("\\ADDR"), is_same_addr);
-						merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->get("\\EN")));
+						module->addEq(NEW_ID, addr, wr_ports[j]->getPort("\\ADDR"), is_same_addr);
+						merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort("\\EN")));
 					}
 				}
 
 				// Then we need to merge the (masked) EN and the DATA signals.
 
-				RTLIL::SigSpec merged_data = wr_ports[last_i]->get("\\DATA");
+				RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort("\\DATA");
 				if (found_overlapping_bits) {
 					log("      Creating logic for merging DATA and EN ports.\n");
-					merge_en_data(merged_en, merged_data, sigmap(cell->get("\\EN")), sigmap(cell->get("\\DATA")));
+					merge_en_data(merged_en, merged_data, sigmap(cell->getPort("\\EN")), sigmap(cell->getPort("\\DATA")));
 				} else {
-					RTLIL::SigSpec cell_en = sigmap(cell->get("\\EN"));
-					RTLIL::SigSpec cell_data = sigmap(cell->get("\\DATA"));
+					RTLIL::SigSpec cell_en = sigmap(cell->getPort("\\EN"));
+					RTLIL::SigSpec cell_data = sigmap(cell->getPort("\\DATA"));
 					for (int k = 0; k < int(en_bits.size()); k++)
 						if (!active_bits_on_port[last_i][k]) {
 							merged_en.replace(k, cell_en.extract(k, 1));
@@ -452,14 +452,14 @@ struct MemoryShareWorker
 
 				// Connect the new EN and DATA signals and remove the old write port.
 
-				cell->set("\\EN", merged_en);
-				cell->set("\\DATA", merged_data);
+				cell->setPort("\\EN", merged_en);
+				cell->setPort("\\DATA", merged_data);
 
 				module->remove(wr_ports[last_i]);
 				wr_ports[last_i] = NULL;
 
 				log("      Active bits: ");
-				std::vector<RTLIL::SigBit> en_bits = sigmap(cell->get("\\EN"));
+				std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN"));
 				active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
 				for (int k = int(en_bits.size())-1; k >= 0; k--)
 					log("%c", active_bits_on_port[i][k] ? '1' : '0');
@@ -498,7 +498,7 @@ struct MemoryShareWorker
 		std::set<int> considered_port_pairs;
 
 		for (int i = 0; i < int(wr_ports.size()); i++) {
-			std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->get("\\EN"));
+			std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
 			for (auto bit : bits)
 				if (bit == RTLIL::State::S1)
 					goto port_is_always_active;
@@ -518,12 +518,12 @@ struct MemoryShareWorker
 			RTLIL::Cell *cell = wr_ports.at(i);
 
 			if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
-					(cache_clk_enable && (sigmap(cell->get("\\CLK")) != cache_clk ||
+					(cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk ||
 					cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
 			{
 				cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
 				cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
-				cache_clk = sigmap(cell->get("\\CLK"));
+				cache_clk = sigmap(cell->getPort("\\CLK"));
 			}
 			else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
 				considered_port_pairs.insert(i);
@@ -551,7 +551,7 @@ struct MemoryShareWorker
 		for (int i = 0; i < int(wr_ports.size()); i++)
 			if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
 			{
-				RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->get("\\EN"));
+				RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
 				port_to_sat_variable[i] = ez.expression(ez.OpOr, satgen.importSigSpec(sig));
 
 				std::vector<RTLIL::SigBit> bits = sig;
@@ -594,18 +594,18 @@ struct MemoryShareWorker
 			log("  Merging port %d into port %d.\n", i-1, i);
 			port_to_sat_variable.at(i) = ez.OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
 
-			RTLIL::SigSpec last_addr = wr_ports[i-1]->get("\\ADDR");
-			RTLIL::SigSpec last_data = wr_ports[i-1]->get("\\DATA");
-			std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->get("\\EN"));
+			RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR");
+			RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA");
+			std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort("\\EN"));
 
-			RTLIL::SigSpec this_addr = wr_ports[i]->get("\\ADDR");
-			RTLIL::SigSpec this_data = wr_ports[i]->get("\\DATA");
-			std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->get("\\EN"));
+			RTLIL::SigSpec this_addr = wr_ports[i]->getPort("\\ADDR");
+			RTLIL::SigSpec this_data = wr_ports[i]->getPort("\\DATA");
+			std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
 
 			RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
 
-			wr_ports[i]->set("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
-			wr_ports[i]->set("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
+			wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
+			wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
 
 			std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
 			RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
@@ -623,7 +623,7 @@ struct MemoryShareWorker
 			}
 
 			module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
-			wr_ports[i]->set("\\EN", en);
+			wr_ports[i]->setPort("\\EN", en);
 
 			module->remove(wr_ports[i-1]);
 			wr_ports[i-1] = NULL;
@@ -662,18 +662,18 @@ struct MemoryShareWorker
 
 			if (cell->type == "$mux")
 			{
-				RTLIL::SigSpec sig_a = sigmap_xmux(cell->get("\\A"));
-				RTLIL::SigSpec sig_b = sigmap_xmux(cell->get("\\B"));
+				RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort("\\A"));
+				RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort("\\B"));
 
 				if (sig_a.is_fully_undef())
-					sigmap_xmux.add(cell->get("\\Y"), sig_b);
+					sigmap_xmux.add(cell->getPort("\\Y"), sig_b);
 				else if (sig_b.is_fully_undef())
-					sigmap_xmux.add(cell->get("\\Y"), sig_a);
+					sigmap_xmux.add(cell->getPort("\\Y"), sig_a);
 			}
 
 			if (cell->type == "$mux" || cell->type == "$pmux")
 			{
-				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->get("\\Y"));
+				std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
 				for (int i = 0; i < int(sig_y.size()); i++)
 					sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
 			}
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index 3f675edea..68e9a9697 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -53,9 +53,9 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
 		cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
-		cell->set("\\CLK", memory->get("\\RD_CLK").extract(i, 1));
-		cell->set("\\ADDR", memory->get("\\RD_ADDR").extract(i*abits, abits));
-		cell->set("\\DATA", memory->get("\\RD_DATA").extract(i*mem->width, mem->width));
+		cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1));
+		cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits));
+		cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width));
 	}
 
 	for (int i = 0; i < num_wr_ports; i++)
@@ -67,10 +67,10 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
 		cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
 		cell->parameters["\\PRIORITY"] = i;
-		cell->set("\\CLK", memory->get("\\WR_CLK").extract(i, 1));
-		cell->set("\\EN", memory->get("\\WR_EN").extract(i*mem->width, mem->width));
-		cell->set("\\ADDR", memory->get("\\WR_ADDR").extract(i*abits, abits));
-		cell->set("\\DATA", memory->get("\\WR_DATA").extract(i*mem->width, mem->width));
+		cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1));
+		cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width));
+		cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits));
+		cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
 	}
 
 	module->remove(memory);
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 3e7487c39..5dab5ecab 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -73,7 +73,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 
 static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
 {
-	RTLIL::SigSpec Y = cell->get(out_port);
+	RTLIL::SigSpec Y = cell->getPort(out_port);
 	out_val.extend_u0(Y.size(), false);
 
 	log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
@@ -89,14 +89,14 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell
 
 static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap)
 {
-	std::string b_name = cell->has("\\B") ? "\\B" : "\\A";
+	std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
 
 	bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
 	bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool();
 
-	RTLIL::SigSpec sig_a = sigmap(cell->get("\\A"));
-	RTLIL::SigSpec sig_b = sigmap(cell->get(b_name));
-	RTLIL::SigSpec sig_y = sigmap(cell->get("\\Y"));
+	RTLIL::SigSpec sig_a = sigmap(cell->getPort("\\A"));
+	RTLIL::SigSpec sig_b = sigmap(cell->getPort(b_name));
+	RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
 
 	if (extend_u0) {
 		sig_a.extend_u0(sig_y.size(), a_signed);
@@ -161,17 +161,17 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 
 		RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
 
-		c->set("\\A", new_a);
+		c->setPort("\\A", new_a);
 		c->parameters["\\A_WIDTH"] = new_a.size();
 		c->parameters["\\A_SIGNED"] = false;
 
 		if (b_name == "\\B") {
-			c->set("\\B", new_b);
+			c->setPort("\\B", new_b);
 			c->parameters["\\B_WIDTH"] = new_b.size();
 			c->parameters["\\B_SIGNED"] = false;
 		}
 
-		c->set("\\Y", new_y);
+		c->setPort("\\Y", new_y);
 		c->parameters["\\Y_WIDTH"] = new_y->width;
 		c->check();
 
@@ -210,8 +210,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 	for (auto cell : module->cells())
 		if (design->selected(module, cell) && cell->type[0] == '$') {
 			if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") &&
-					cell->get("\\A").size() == 1 && cell->get("\\Y").size() == 1)
-				invert_map[assign_map(cell->get("\\Y"))] = assign_map(cell->get("\\A"));
+					cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1)
+				invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A"));
 			if (ct_combinational.cell_known(cell->type))
 				for (auto &conn : cell->connections()) {
 					RTLIL::SigSpec sig = assign_map(conn.second);
@@ -246,7 +246,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$reduce_and")
 			{
-				RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
+				RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 
 				RTLIL::State new_a = RTLIL::State::S1;
 				for (auto &bit : sig_a.to_sigbit_vector())
@@ -264,7 +264,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover("opt.opt_const.fine.$reduce_and");
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->set("\\A", sig_a = new_a);
+					cell->setPort("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -273,7 +273,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$logic_not" || cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$reduce_or" || cell->type == "$reduce_bool")
 			{
-				RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
+				RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 
 				RTLIL::State new_a = RTLIL::State::S0;
 				for (auto &bit : sig_a.to_sigbit_vector())
@@ -291,7 +291,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->set("\\A", sig_a = new_a);
+					cell->setPort("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -300,7 +300,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$logic_and" || cell->type == "$logic_or")
 			{
-				RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
+				RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
 
 				RTLIL::State new_b = RTLIL::State::S0;
 				for (auto &bit : sig_b.to_sigbit_vector())
@@ -318,7 +318,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
 					log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
-					cell->set("\\B", sig_b = new_b);
+					cell->setPort("\\B", sig_b = new_b);
 					cell->parameters.at("\\B_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -326,13 +326,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 		}
 
-		if (cell->type == "$logic_or" && (assign_map(cell->get("\\A")) == RTLIL::State::S1 || assign_map(cell->get("\\B")) == RTLIL::State::S1)) {
+		if (cell->type == "$logic_or" && (assign_map(cell->getPort("\\A")) == RTLIL::State::S1 || assign_map(cell->getPort("\\B")) == RTLIL::State::S1)) {
 			cover("opt.opt_const.one_high");
 			replace_cell(assign_map, module, cell, "one high", "\\Y", RTLIL::State::S1);
 			goto next_cell;
 		}
 
-		if (cell->type == "$logic_and" && (assign_map(cell->get("\\A")) == RTLIL::State::S0 || assign_map(cell->get("\\B")) == RTLIL::State::S0)) {
+		if (cell->type == "$logic_and" && (assign_map(cell->getPort("\\A")) == RTLIL::State::S0 || assign_map(cell->getPort("\\B")) == RTLIL::State::S0)) {
 			cover("opt.opt_const.one_low");
 			replace_cell(assign_map, module, cell, "one low", "\\Y", RTLIL::State::S0);
 			goto next_cell;
@@ -344,8 +344,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
 				cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
 		{
-			RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-			RTLIL::SigSpec sig_b = cell->has("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec();
+			RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+			RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec();
 
 			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
 				sig_a = RTLIL::SigSpec();
@@ -366,31 +366,31 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 						cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
 					replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
 				else
-					replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->get("\\Y").size()));
+					replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort("\\Y").size()));
 				goto next_cell;
 			}
 		}
 
-		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->get("\\Y").size() == 1 &&
-				invert_map.count(assign_map(cell->get("\\A"))) != 0) {
+		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 &&
+				invert_map.count(assign_map(cell->getPort("\\A"))) != 0) {
 			cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type);
-			replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->get("\\A"))));
+			replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A"))));
 			goto next_cell;
 		}
 
-		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->get("\\S"))) != 0) {
+		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
 			cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type);
-			RTLIL::SigSpec tmp = cell->get("\\A");
-			cell->set("\\A", cell->get("\\B"));
-			cell->set("\\B", tmp);
-			cell->set("\\S", invert_map.at(assign_map(cell->get("\\S"))));
+			RTLIL::SigSpec tmp = cell->getPort("\\A");
+			cell->setPort("\\A", cell->getPort("\\B"));
+			cell->setPort("\\B", tmp);
+			cell->setPort("\\S", invert_map.at(assign_map(cell->getPort("\\S"))));
 			OPT_DID_SOMETHING = true;
 			did_something = true;
 			goto next_cell;
 		}
 
 		if (cell->type == "$_INV_") {
-			RTLIL::SigSpec input = cell->get("\\A");
+			RTLIL::SigSpec input = cell->getPort("\\A");
 			assign_map.apply(input);
 			if (input.match("1")) ACTION_DO_Y(0);
 			if (input.match("0")) ACTION_DO_Y(1);
@@ -399,8 +399,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_AND_") {
 			RTLIL::SigSpec input;
-			input.append(cell->get("\\B"));
-			input.append(cell->get("\\A"));
+			input.append(cell->getPort("\\B"));
+			input.append(cell->getPort("\\A"));
 			assign_map.apply(input);
 			if (input.match(" 0")) ACTION_DO_Y(0);
 			if (input.match("0 ")) ACTION_DO_Y(0);
@@ -418,8 +418,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_OR_") {
 			RTLIL::SigSpec input;
-			input.append(cell->get("\\B"));
-			input.append(cell->get("\\A"));
+			input.append(cell->getPort("\\B"));
+			input.append(cell->getPort("\\A"));
 			assign_map.apply(input);
 			if (input.match(" 1")) ACTION_DO_Y(1);
 			if (input.match("1 ")) ACTION_DO_Y(1);
@@ -437,8 +437,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_XOR_") {
 			RTLIL::SigSpec input;
-			input.append(cell->get("\\B"));
-			input.append(cell->get("\\A"));
+			input.append(cell->getPort("\\B"));
+			input.append(cell->getPort("\\A"));
 			assign_map.apply(input);
 			if (input.match("00")) ACTION_DO_Y(0);
 			if (input.match("01")) ACTION_DO_Y(1);
@@ -452,9 +452,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$_MUX_") {
 			RTLIL::SigSpec input;
-			input.append(cell->get("\\S"));
-			input.append(cell->get("\\B"));
-			input.append(cell->get("\\A"));
+			input.append(cell->getPort("\\S"));
+			input.append(cell->getPort("\\B"));
+			input.append(cell->getPort("\\A"));
 			assign_map.apply(input);
 			if (input.extract(2, 1) == input.extract(1, 1))
 				ACTION_DO("\\Y", input.extract(2, 1));
@@ -464,9 +464,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			if (input.match("10 ")) {
 				cover("opt.opt_const.mux_to_inv");
 				cell->type = "$_INV_";
-				cell->set("\\A", input.extract(0, 1));
-				cell->unset("\\B");
-				cell->unset("\\S");
+				cell->setPort("\\A", input.extract(0, 1));
+				cell->unsetPort("\\B");
+				cell->unsetPort("\\S");
 				goto next_cell;
 			}
 			if (input.match("11 ")) ACTION_DO_Y(1);
@@ -483,8 +483,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex")
 		{
-			RTLIL::SigSpec a = cell->get("\\A");
-			RTLIL::SigSpec b = cell->get("\\B");
+			RTLIL::SigSpec a = cell->getPort("\\A");
+			RTLIL::SigSpec b = cell->getPort("\\B");
 
 			if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
 				int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
@@ -519,8 +519,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (new_a.size() < a.size() || new_b.size() < b.size()) {
 				cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type);
-				cell->set("\\A", new_a);
-				cell->set("\\B", new_b);
+				cell->setPort("\\A", new_a);
+				cell->setPort("\\B", new_b);
 				cell->parameters["\\A_WIDTH"] = new_a.size();
 				cell->parameters["\\B_WIDTH"] = new_b.size();
 			}
@@ -529,26 +529,26 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
 				cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
 		{
-			RTLIL::SigSpec a = assign_map(cell->get("\\A"));
-			RTLIL::SigSpec b = assign_map(cell->get("\\B"));
+			RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
+			RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
 
 			if (a.is_fully_const()) {
 				cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
-				RTLIL::SigSpec tmp = cell->get("\\A");
-				cell->set("\\A", cell->get("\\B"));
-				cell->set("\\B", tmp);
+				RTLIL::SigSpec tmp = cell->getPort("\\A");
+				cell->setPort("\\A", cell->getPort("\\B"));
+				cell->setPort("\\B", tmp);
 			}
 
 			if (b.is_fully_const()) {
 				if (b.as_bool() == (cell->type == "$eq")) {
 					RTLIL::SigSpec input = b;
-					ACTION_DO("\\Y", cell->get("\\A"));
+					ACTION_DO("\\Y", cell->getPort("\\A"));
 				} else {
 					cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type);
 					cell->type = "$not";
 					cell->parameters.erase("\\B_WIDTH");
 					cell->parameters.erase("\\B_SIGNED");
-					cell->unset("\\B");
+					cell->unsetPort("\\B");
 				}
 				goto next_cell;
 			}
@@ -562,8 +562,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$add" || cell->type == "$sub" || cell->type == "$or" || cell->type == "$xor")
 			{
-				RTLIL::SigSpec a = assign_map(cell->get("\\A"));
-				RTLIL::SigSpec b = assign_map(cell->get("\\B"));
+				RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
+				RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
 
 				if (cell->type != "$sub" && a.is_fully_const() && a.as_bool() == false)
 					identity_wrt_b = true;
@@ -574,7 +574,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
 			{
-				RTLIL::SigSpec b = assign_map(cell->get("\\B"));
+				RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
 
 				if (b.is_fully_const() && b.as_bool() == false)
 					identity_wrt_a = true, identity_bu0 = true;
@@ -582,8 +582,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$mul")
 			{
-				RTLIL::SigSpec a = assign_map(cell->get("\\A"));
-				RTLIL::SigSpec b = assign_map(cell->get("\\B"));
+				RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
+				RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
 
 				if (a.is_fully_const() && a.size() <= 32 && a.as_int() == 1)
 					identity_wrt_b = true;
@@ -594,7 +594,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (cell->type == "$div")
 			{
-				RTLIL::SigSpec b = assign_map(cell->get("\\B"));
+				RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
 
 				if (b.is_fully_const() && b.size() <= 32 && b.as_int() == 1)
 					identity_wrt_a = true;
@@ -611,13 +611,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
 
 				if (!identity_wrt_a) {
-					cell->set("\\A", cell->get("\\B"));
+					cell->setPort("\\A", cell->getPort("\\B"));
 					cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
 					cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
 				}
 
 				cell->type = identity_bu0 ? "$bu0" : "$pos";
-				cell->unset("\\B");
+				cell->unsetPort("\\B");
 				cell->parameters.erase("\\B_WIDTH");
 				cell->parameters.erase("\\B_SIGNED");
 				cell->check();
@@ -629,18 +629,18 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		}
 
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
-				cell->get("\\A") == RTLIL::SigSpec(0, 1) && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
+				cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type);
-			replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->get("\\S"));
+			replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S"));
 			goto next_cell;
 		}
 
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
-				cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) {
+				cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
-			cell->set("\\A", cell->get("\\S"));
-			cell->unset("\\B");
-			cell->unset("\\S");
+			cell->setPort("\\A", cell->getPort("\\S"));
+			cell->unsetPort("\\B");
+			cell->unsetPort("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -654,10 +654,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) {
+		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
-			cell->set("\\A", cell->get("\\S"));
-			cell->unset("\\S");
+			cell->setPort("\\A", cell->getPort("\\S"));
+			cell->unsetPort("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -673,10 +673,10 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			goto next_cell;
 		}
 
-		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
+		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
-			cell->set("\\B", cell->get("\\S"));
-			cell->unset("\\S");
+			cell->setPort("\\B", cell->getPort("\\S"));
+			cell->unsetPort("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -694,22 +694,22 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
 			RTLIL::SigSpec new_a, new_b, new_s;
-			int width = cell->get("\\A").size();
-			if ((cell->get("\\A").is_fully_undef() && cell->get("\\B").is_fully_undef()) ||
-					cell->get("\\S").is_fully_undef()) {
+			int width = cell->getPort("\\A").size();
+			if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) ||
+					cell->getPort("\\S").is_fully_undef()) {
 				cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type);
-				replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->get("\\A"));
+				replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->getPort("\\A"));
 				goto next_cell;
 			}
-			for (int i = 0; i < cell->get("\\S").size(); i++) {
-				RTLIL::SigSpec old_b = cell->get("\\B").extract(i*width, width);
-				RTLIL::SigSpec old_s = cell->get("\\S").extract(i, 1);
+			for (int i = 0; i < cell->getPort("\\S").size(); i++) {
+				RTLIL::SigSpec old_b = cell->getPort("\\B").extract(i*width, width);
+				RTLIL::SigSpec old_s = cell->getPort("\\S").extract(i, 1);
 				if (old_b.is_fully_undef() || old_s.is_fully_undef())
 					continue;
 				new_b.append(old_b);
 				new_s.append(old_s);
 			}
-			new_a = cell->get("\\A");
+			new_a = cell->getPort("\\A");
 			if (new_a.is_fully_undef() && new_s.size() > 0) {
 				new_a = new_b.extract((new_s.size()-1)*width, width);
 				new_b = new_b.extract(0, (new_s.size()-1)*width);
@@ -725,11 +725,11 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s);
 				goto next_cell;
 			}
-			if (cell->get("\\S").size() != new_s.size()) {
+			if (cell->getPort("\\S").size() != new_s.size()) {
 				cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
-				cell->set("\\A", new_a);
-				cell->set("\\B", new_b);
-				cell->set("\\S", new_s);
+				cell->setPort("\\A", new_a);
+				cell->setPort("\\B", new_b);
+				cell->setPort("\\S", new_s);
 				if (new_s.size() > 1) {
 					cell->type = "$pmux";
 					cell->parameters["\\S_WIDTH"] = new_s.size();
@@ -744,7 +744,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 #define FOLD_1ARG_CELL(_t) \
 		if (cell->type == "$" #_t) { \
-			RTLIL::SigSpec a = cell->get("\\A"); \
+			RTLIL::SigSpec a = cell->getPort("\\A"); \
 			assign_map.apply(a); \
 			if (a.is_fully_const()) { \
 				RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
@@ -758,8 +758,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		}
 #define FOLD_2ARG_CELL(_t) \
 		if (cell->type == "$" #_t) { \
-			RTLIL::SigSpec a = cell->get("\\A"); \
-			RTLIL::SigSpec b = cell->get("\\B"); \
+			RTLIL::SigSpec a = cell->getPort("\\A"); \
+			RTLIL::SigSpec b = cell->getPort("\\B"); \
 			assign_map.apply(a), assign_map.apply(b); \
 			if (a.is_fully_const() && b.is_fully_const()) { \
 				RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
@@ -815,13 +815,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		// be very conservative with optimizing $mux cells as we do not want to break mux trees
 		if (cell->type == "$mux") {
-			RTLIL::SigSpec input = assign_map(cell->get("\\S"));
-			RTLIL::SigSpec inA = assign_map(cell->get("\\A"));
-			RTLIL::SigSpec inB = assign_map(cell->get("\\B"));
+			RTLIL::SigSpec input = assign_map(cell->getPort("\\S"));
+			RTLIL::SigSpec inA = assign_map(cell->getPort("\\A"));
+			RTLIL::SigSpec inB = assign_map(cell->getPort("\\B"));
 			if (input.is_fully_const())
-				ACTION_DO("\\Y", input.as_bool() ? cell->get("\\B") : cell->get("\\A"));
+				ACTION_DO("\\Y", input.as_bool() ? cell->getPort("\\B") : cell->getPort("\\A"));
 			else if (inA == inB)
-				ACTION_DO("\\Y", cell->get("\\A"));
+				ACTION_DO("\\Y", cell->getPort("\\A"));
 		}
 
 		if (!keepdc && cell->type == "$mul")
@@ -830,9 +830,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			bool b_signed = cell->parameters["\\B_SIGNED"].as_bool();
 			bool swapped_ab = false;
 
-			RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-			RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-			RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
+			RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+			RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+			RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
 
 			if (sig_b.is_fully_const() && sig_b.size() <= 32)
 				std::swap(sig_a, sig_b), std::swap(a_signed, b_signed), swapped_ab = true;
@@ -868,7 +868,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 								a_val, cell->name.c_str(), module->name.c_str(), i);
 
 						if (!swapped_ab) {
-							cell->set("\\A", cell->get("\\B"));
+							cell->setPort("\\A", cell->getPort("\\B"));
 							cell->parameters["\\A_WIDTH"] = cell->parameters["\\B_WIDTH"];
 							cell->parameters["\\A_SIGNED"] = cell->parameters["\\B_SIGNED"];
 						}
@@ -881,7 +881,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 						cell->type = "$shl";
 						cell->parameters["\\B_WIDTH"] = SIZE(new_b);
 						cell->parameters["\\B_SIGNED"] = false;
-						cell->set("\\B", new_b);
+						cell->setPort("\\B", new_b);
 						cell->check();
 
 						OPT_DID_SOMETHING = true;
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index de12542dc..2660b33d4 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -86,10 +86,10 @@ struct OptMuxtreeWorker
 		{
 			if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
 			{
-				RTLIL::SigSpec sig_a = cell->get("\\A");
-				RTLIL::SigSpec sig_b = cell->get("\\B");
-				RTLIL::SigSpec sig_s = cell->get("\\S");
-				RTLIL::SigSpec sig_y = cell->get("\\Y");
+				RTLIL::SigSpec sig_a = cell->getPort("\\A");
+				RTLIL::SigSpec sig_b = cell->getPort("\\B");
+				RTLIL::SigSpec sig_s = cell->getPort("\\S");
+				RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 				muxinfo_t muxinfo;
 				muxinfo.cell = cell;
@@ -192,10 +192,10 @@ struct OptMuxtreeWorker
 				continue;
 			}
 
-			RTLIL::SigSpec sig_a = mi.cell->get("\\A");
-			RTLIL::SigSpec sig_b = mi.cell->get("\\B");
-			RTLIL::SigSpec sig_s = mi.cell->get("\\S");
-			RTLIL::SigSpec sig_y = mi.cell->get("\\Y");
+			RTLIL::SigSpec sig_a = mi.cell->getPort("\\A");
+			RTLIL::SigSpec sig_b = mi.cell->getPort("\\B");
+			RTLIL::SigSpec sig_s = mi.cell->getPort("\\S");
+			RTLIL::SigSpec sig_y = mi.cell->getPort("\\Y");
 
 			RTLIL::SigSpec sig_ports = sig_b;
 			sig_ports.append(sig_a);
@@ -220,9 +220,9 @@ struct OptMuxtreeWorker
 					}
 				}
 
-				mi.cell->set("\\A", new_sig_a);
-				mi.cell->set("\\B", new_sig_b);
-				mi.cell->set("\\S", new_sig_s);
+				mi.cell->setPort("\\A", new_sig_a);
+				mi.cell->setPort("\\B", new_sig_b);
+				mi.cell->setPort("\\S", new_sig_s);
 				if (new_sig_s.size() == 1) {
 					mi.cell->type = "$mux";
 					mi.cell->parameters.erase("\\S_WIDTH");
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 8aadd1f23..80ec89744 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -42,7 +42,7 @@ struct OptReduceWorker
 			return;
 		cells.erase(cell);
 
-		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
+		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
 		std::set<RTLIL::SigBit> new_sig_a_bits;
 
 		for (auto &bit : sig_a.to_sigbit_set())
@@ -72,8 +72,8 @@ struct OptReduceWorker
 			for (auto child_cell : drivers.find(bit)) {
 				if (child_cell->type == cell->type) {
 					opt_reduce(cells, drivers, child_cell);
-					if (child_cell->get("\\Y")[0] == bit) {
-						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->get("\\A")).to_sigbit_set();
+					if (child_cell->getPort("\\Y")[0] == bit) {
+						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort("\\A")).to_sigbit_set();
 						new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
 					} else
 						new_sig_a_bits.insert(RTLIL::State::S0);
@@ -86,23 +86,23 @@ struct OptReduceWorker
 
 		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 
-		if (new_sig_a != sig_a || sig_a.size() != cell->get("\\A").size()) {
+		if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
 			did_something = true;
 			OPT_DID_SOMETHING = true;
 			total_count++;
 		}
 
-		cell->set("\\A", new_sig_a);
+		cell->setPort("\\A", new_sig_a);
 		cell->parameters["\\A_WIDTH"] = RTLIL::Const(new_sig_a.size());
 		return;
 	}
 
 	void opt_mux(RTLIL::Cell *cell)
 	{
-		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));
+		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+		RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
 
 		RTLIL::SigSpec new_sig_b, new_sig_s;
 		std::set<RTLIL::SigSpec> handled_sig;
@@ -124,14 +124,14 @@ struct OptReduceWorker
 			if (this_s.size() > 1)
 			{
 				RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
-				reduce_or_cell->set("\\A", this_s);
+				reduce_or_cell->setPort("\\A", this_s);
 				reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 				reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
 				reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
 				RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
 				this_s = RTLIL::SigSpec(reduce_or_wire);
-				reduce_or_cell->set("\\Y", this_s);
+				reduce_or_cell->setPort("\\Y", this_s);
 			}
 
 			new_sig_b.append(this_b);
@@ -148,14 +148,14 @@ struct OptReduceWorker
 
 		if (new_sig_s.size() == 0)
 		{
-			module->connect(RTLIL::SigSig(cell->get("\\Y"), cell->get("\\A")));
-			assign_map.add(cell->get("\\Y"), cell->get("\\A"));
+			module->connect(RTLIL::SigSig(cell->getPort("\\Y"), cell->getPort("\\A")));
+			assign_map.add(cell->getPort("\\Y"), cell->getPort("\\A"));
 			module->remove(cell);
 		}
 		else
 		{
-			cell->set("\\B", new_sig_b);
-			cell->set("\\S", new_sig_s);
+			cell->setPort("\\B", new_sig_b);
+			cell->setPort("\\S", new_sig_s);
 			if (new_sig_s.size() > 1) {
 				cell->parameters["\\S_WIDTH"] = RTLIL::Const(new_sig_s.size());
 			} else {
@@ -167,9 +167,9 @@ struct OptReduceWorker
 
 	void opt_mux_bits(RTLIL::Cell *cell)
 	{
-		std::vector<RTLIL::SigBit> sig_a = assign_map(cell->get("\\A")).to_sigbit_vector();
-		std::vector<RTLIL::SigBit> sig_b = assign_map(cell->get("\\B")).to_sigbit_vector();
-		std::vector<RTLIL::SigBit> sig_y = assign_map(cell->get("\\Y")).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort("\\A")).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort("\\B")).to_sigbit_vector();
+		std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort("\\Y")).to_sigbit_vector();
 
 		std::vector<RTLIL::SigBit> new_sig_y;
 		RTLIL::SigSig old_sig_conn;
@@ -210,29 +210,29 @@ struct OptReduceWorker
 		if (new_sig_y.size() != sig_y.size())
 		{
 			log("    Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
-			log("      Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")),
-					log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
+			log("      Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
+					log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
 
-			cell->set("\\A", RTLIL::SigSpec());
+			cell->setPort("\\A", RTLIL::SigSpec());
 			for (auto &in_tuple : consolidated_in_tuples) {
-				RTLIL::SigSpec new_a = cell->get("\\A");
+				RTLIL::SigSpec new_a = cell->getPort("\\A");
 				new_a.append(in_tuple.at(0));
-				cell->set("\\A", new_a);
+				cell->setPort("\\A", new_a);
 			}
 
-			cell->set("\\B", RTLIL::SigSpec());
-			for (int i = 1; i <= cell->get("\\S").size(); i++)
+			cell->setPort("\\B", RTLIL::SigSpec());
+			for (int i = 1; i <= cell->getPort("\\S").size(); i++)
 				for (auto &in_tuple : consolidated_in_tuples) {
-					RTLIL::SigSpec new_b = cell->get("\\B");
+					RTLIL::SigSpec new_b = cell->getPort("\\B");
 					new_b.append(in_tuple.at(i));
-					cell->set("\\B", new_b);
+					cell->setPort("\\B", new_b);
 				}
 
 			cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
-			cell->set("\\Y", new_sig_y);
+			cell->setPort("\\Y", new_sig_y);
 
-			log("      New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->get("\\A")),
-					log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
+			log("      New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort("\\A")),
+					log_signal(cell->getPort("\\B")), log_signal(cell->getPort("\\Y")));
 			log("      New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
 
 			module->connect(old_sig_conn);
@@ -256,14 +256,14 @@ struct OptReduceWorker
 		for (auto &cell_it : module->cells_) {
 			RTLIL::Cell *cell = cell_it.second;
 			if (cell->type == "$mem")
-				mem_wren_sigs.add(assign_map(cell->get("\\WR_EN")));
+				mem_wren_sigs.add(assign_map(cell->getPort("\\WR_EN")));
 			if (cell->type == "$memwr")
-				mem_wren_sigs.add(assign_map(cell->get("\\EN")));
+				mem_wren_sigs.add(assign_map(cell->getPort("\\EN")));
 		}
 		for (auto &cell_it : module->cells_) {
 			RTLIL::Cell *cell = cell_it.second;
-			if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q"))))
-				mem_wren_sigs.add(assign_map(cell->get("\\D")));
+			if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Q"))))
+				mem_wren_sigs.add(assign_map(cell->getPort("\\D")));
 		}
 
 		bool keep_expanding_mem_wren_sigs = true;
@@ -271,12 +271,12 @@ struct OptReduceWorker
 			keep_expanding_mem_wren_sigs = false;
 			for (auto &cell_it : module->cells_) {
 				RTLIL::Cell *cell = cell_it.second;
-				if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) {
-					if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) ||
-							!mem_wren_sigs.check_all(assign_map(cell->get("\\B"))))
+				if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y")))) {
+					if (!mem_wren_sigs.check_all(assign_map(cell->getPort("\\A"))) ||
+							!mem_wren_sigs.check_all(assign_map(cell->getPort("\\B"))))
 						keep_expanding_mem_wren_sigs = true;
-					mem_wren_sigs.add(assign_map(cell->get("\\A")));
-					mem_wren_sigs.add(assign_map(cell->get("\\B")));
+					mem_wren_sigs.add(assign_map(cell->getPort("\\A")));
+					mem_wren_sigs.add(assign_map(cell->getPort("\\B")));
 				}
 			}
 		}
@@ -298,7 +298,7 @@ struct OptReduceWorker
 					RTLIL::Cell *cell = cell_it.second;
 					if (cell->type != type || !design->selected(module, cell))
 						continue;
-					drivers.insert(assign_map(cell->get("\\Y")), cell);
+					drivers.insert(assign_map(cell->getPort("\\Y")), cell);
 					cells.insert(cell);
 				}
 
@@ -320,7 +320,7 @@ struct OptReduceWorker
 			{
 				// this optimization is to aggressive for most coarse-grain applications.
 				// but we always want it for multiplexers driving write enable ports.
-				if (do_fine || mem_wren_sigs.check_any(assign_map(cell->get("\\Y"))))
+				if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort("\\Y"))))
 					opt_mux_bits(cell);
 
 				opt_mux(cell);
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index b01778b5e..c1e33caf3 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -33,34 +33,34 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 	RTLIL::Const val_cp, val_rp, val_rv;
 
 	if (dff->type == "$_DFF_N_" || dff->type == "$_DFF_P_") {
-		sig_d = dff->get("\\D");
-		sig_q = dff->get("\\Q");
-		sig_c = dff->get("\\C");
+		sig_d = dff->getPort("\\D");
+		sig_q = dff->getPort("\\Q");
+		sig_c = dff->getPort("\\C");
 		val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
 	}
 	else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" &&
 			(dff->type[6] == 'N' || dff->type[6] == 'P') &&
 			(dff->type[7] == 'N' || dff->type[7] == 'P') &&
 			(dff->type[8] == '0' || dff->type[8] == '1')) {
-		sig_d = dff->get("\\D");
-		sig_q = dff->get("\\Q");
-		sig_c = dff->get("\\C");
-		sig_r = dff->get("\\R");
+		sig_d = dff->getPort("\\D");
+		sig_q = dff->getPort("\\Q");
+		sig_c = dff->getPort("\\C");
+		sig_r = dff->getPort("\\R");
 		val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
 		val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
 		val_rv = RTLIL::Const(dff->type[8] == '1', 1);
 	}
 	else if (dff->type == "$dff") {
-		sig_d = dff->get("\\D");
-		sig_q = dff->get("\\Q");
-		sig_c = dff->get("\\CLK");
+		sig_d = dff->getPort("\\D");
+		sig_q = dff->getPort("\\Q");
+		sig_c = dff->getPort("\\CLK");
 		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
 	}
 	else if (dff->type == "$adff") {
-		sig_d = dff->get("\\D");
-		sig_q = dff->get("\\Q");
-		sig_c = dff->get("\\CLK");
-		sig_r = dff->get("\\ARST");
+		sig_d = dff->getPort("\\D");
+		sig_q = dff->getPort("\\Q");
+		sig_c = dff->getPort("\\CLK");
+		sig_r = dff->getPort("\\ARST");
 		val_cp = RTLIL::Const(dff->parameters["\\CLK_POLARITY"].as_bool(), 1);
 		val_rp = RTLIL::Const(dff->parameters["\\ARST_POLARITY"].as_bool(), 1);
 		val_rv = dff->parameters["\\ARST_VALUE"];
@@ -85,8 +85,8 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		std::set<RTLIL::Cell*> muxes;
 		mux_drivers.find(sig_d, muxes);
 		for (auto mux : muxes) {
-			RTLIL::SigSpec sig_a = assign_map(mux->get("\\A"));
-			RTLIL::SigSpec sig_b = assign_map(mux->get("\\B"));
+			RTLIL::SigSpec sig_a = assign_map(mux->getPort("\\A"));
+			RTLIL::SigSpec sig_b = assign_map(mux->getPort("\\B"));
 			if (sig_a == sig_q && sig_b.is_fully_const()) {
 				RTLIL::SigSig conn(sig_q, sig_b);
 				mod->connect(conn);
@@ -181,8 +181,8 @@ struct OptRmdffPass : public Pass {
 			std::vector<std::string> dff_list;
 			for (auto &it : mod_it.second->cells_) {
 				if (it.second->type == "$mux" || it.second->type == "$pmux") {
-					if (it.second->get("\\A").size() == it.second->get("\\B").size())
-						mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second);
+					if (it.second->getPort("\\A").size() == it.second->getPort("\\B").size())
+						mux_drivers.insert(assign_map(it.second->getPort("\\Y")), it.second);
 					continue;
 				}
 				if (!design->selected(mod_it.second, it.second))
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index ad6e1a746..26d19414a 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -179,8 +179,8 @@ struct OptShareWorker
 		}
 
 		if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
-			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->get("\\Q")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->get("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector();
 			for (size_t i = 0; i < q1.size(); i++)
 				if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
 					lt = q1.at(i) < q2.at(i);
@@ -262,7 +262,7 @@ struct OptShareWorker
 					log("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
 					for (auto &it : cell->connections()) {
 						if (ct.cell_output(cell->type, it.first)) {
-							RTLIL::SigSpec other_sig = sharemap[cell]->get(it.first);
+							RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
 							log("    Redirecting output %s: %s = %s\n", it.first.c_str(),
 									log_signal(it.second), log_signal(other_sig));
 							module->connect(RTLIL::SigSig(it.second, other_sig));
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 676469fe2..f11b328f0 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -35,45 +35,45 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
 
 	for (auto cell : mod->cells())
 	{
-		if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
-			return check_signal(mod, cell->get("\\A"), ref, polarity);
+		if (cell->type == "$reduce_or" && cell->getPort("\\Y") == signal)
+			return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 
-		if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
-			return check_signal(mod, cell->get("\\A"), ref, polarity);
+		if (cell->type == "$reduce_bool" && cell->getPort("\\Y") == signal)
+			return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 
-		if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
+		if (cell->type == "$logic_not" && cell->getPort("\\Y") == signal) {
 			polarity = !polarity;
-			return check_signal(mod, cell->get("\\A"), ref, polarity);
+			return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 		}
 
-		if (cell->type == "$not" && cell->get("\\Y") == signal) {
+		if (cell->type == "$not" && cell->getPort("\\Y") == signal) {
 			polarity = !polarity;
-			return check_signal(mod, cell->get("\\A"), ref, polarity);
+			return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 		}
 
-		if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
-			if (cell->get("\\A").is_fully_const()) {
-				if (!cell->get("\\A").as_bool())
+		if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) {
+			if (cell->getPort("\\A").is_fully_const()) {
+				if (!cell->getPort("\\A").as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->get("\\B"), ref, polarity);
+				return check_signal(mod, cell->getPort("\\B"), ref, polarity);
 			}
-			if (cell->get("\\B").is_fully_const()) {
-				if (!cell->get("\\B").as_bool())
+			if (cell->getPort("\\B").is_fully_const()) {
+				if (!cell->getPort("\\B").as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->get("\\A"), ref, polarity);
+				return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 			}
 		}
 
-		if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
-			if (cell->get("\\A").is_fully_const()) {
-				if (cell->get("\\A").as_bool())
+		if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) {
+			if (cell->getPort("\\A").is_fully_const()) {
+				if (cell->getPort("\\A").as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->get("\\B"), ref, polarity);
+				return check_signal(mod, cell->getPort("\\B"), ref, polarity);
 			}
-			if (cell->get("\\B").is_fully_const()) {
-				if (cell->get("\\B").as_bool())
+			if (cell->getPort("\\B").is_fully_const()) {
+				if (cell->getPort("\\B").as_bool())
 					polarity = !polarity;
-				return check_signal(mod, cell->get("\\A"), ref, polarity);
+				return check_signal(mod, cell->getPort("\\A"), ref, polarity);
 			}
 		}
 	}
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index d894b442b..e69e8023d 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -76,8 +76,8 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->set("\\A", sync_low_signals);
-			cell->set("\\Y", sync_low_signals = mod->addWire(NEW_ID));
+			cell->setPort("\\A", sync_low_signals);
+			cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID));
 		}
 
 		if (sync_low_signals.size() > 0) {
@@ -85,9 +85,9 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->set("\\A", sync_low_signals);
-			cell->set("\\Y", mod->addWire(NEW_ID));
-			sync_high_signals.append(cell->get("\\Y"));
+			cell->setPort("\\A", sync_low_signals);
+			cell->setPort("\\Y", mod->addWire(NEW_ID));
+			sync_high_signals.append(cell->getPort("\\Y"));
 		}
 
 		if (sync_high_signals.size() > 1) {
@@ -95,30 +95,30 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 			cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 			cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
 			cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-			cell->set("\\A", sync_high_signals);
-			cell->set("\\Y", sync_high_signals = mod->addWire(NEW_ID));
+			cell->setPort("\\A", sync_high_signals);
+			cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID));
 		}
 
 		RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
 		inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 		inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
 		inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
-		inv_cell->set("\\A", sync_value);
-		inv_cell->set("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
+		inv_cell->setPort("\\A", sync_value);
+		inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
 
 		RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
 		mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
-		mux_set_cell->set("\\A", sig_sr_set);
-		mux_set_cell->set("\\B", sync_value);
-		mux_set_cell->set("\\S", sync_high_signals);
-		mux_set_cell->set("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
+		mux_set_cell->setPort("\\A", sig_sr_set);
+		mux_set_cell->setPort("\\B", sync_value);
+		mux_set_cell->setPort("\\S", sync_high_signals);
+		mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
 
 		RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
 		mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
-		mux_clr_cell->set("\\A", sig_sr_clr);
-		mux_clr_cell->set("\\B", sync_value_inv);
-		mux_clr_cell->set("\\S", sync_high_signals);
-		mux_clr_cell->set("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
+		mux_clr_cell->setPort("\\A", sig_sr_clr);
+		mux_clr_cell->setPort("\\B", sync_value_inv);
+		mux_clr_cell->setPort("\\S", sync_high_signals);
+		mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
 	}
 
 	std::stringstream sstr;
@@ -130,11 +130,11 @@ static void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::S
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 	cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
 	cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
-	cell->set("\\D", sig_d);
-	cell->set("\\Q", sig_q);
-	cell->set("\\CLK", clk);
-	cell->set("\\SET", sig_sr_set);
-	cell->set("\\CLR", sig_sr_clr);
+	cell->setPort("\\D", sig_d);
+	cell->setPort("\\Q", sig_q);
+	cell->setPort("\\CLK", clk);
+	cell->setPort("\\SET", sig_sr_set);
+	cell->setPort("\\CLR", sig_sr_clr);
 
 	log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
 			cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@@ -154,22 +154,22 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
 	inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
 	inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
 	inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
-	inv_set->set("\\A", sig_set);
-	inv_set->set("\\Y", sig_set_inv);
+	inv_set->setPort("\\A", sig_set);
+	inv_set->setPort("\\Y", sig_set_inv);
 
 	RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
 	mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
-	mux_sr_set->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
-	mux_sr_set->set(set_polarity ? "\\B" : "\\A", sig_set);
-	mux_sr_set->set("\\Y", sig_sr_set);
-	mux_sr_set->set("\\S", set);
+	mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
+	mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set);
+	mux_sr_set->setPort("\\Y", sig_sr_set);
+	mux_sr_set->setPort("\\S", set);
 
 	RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
 	mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
-	mux_sr_clr->set(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
-	mux_sr_clr->set(set_polarity ? "\\B" : "\\A", sig_set_inv);
-	mux_sr_clr->set("\\Y", sig_sr_clr);
-	mux_sr_clr->set("\\S", set);
+	mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
+	mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv);
+	mux_sr_clr->setPort("\\Y", sig_sr_clr);
+	mux_sr_clr->setPort("\\S", set);
 
 	RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
 	cell->attributes = proc->attributes;
@@ -177,11 +177,11 @@ static void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 	cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
 	cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
-	cell->set("\\D", sig_in);
-	cell->set("\\Q", sig_out);
-	cell->set("\\CLK", clk);
-	cell->set("\\SET", sig_sr_set);
-	cell->set("\\CLR", sig_sr_clr);
+	cell->setPort("\\D", sig_in);
+	cell->setPort("\\Q", sig_out);
+	cell->setPort("\\CLK", clk);
+	cell->setPort("\\SET", sig_sr_set);
+	cell->setPort("\\CLR", sig_sr_clr);
 
 	log("  created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
 			clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
@@ -203,11 +203,11 @@ static void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_
 	}
 	cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
 
-	cell->set("\\D", sig_in);
-	cell->set("\\Q", sig_out);
+	cell->setPort("\\D", sig_in);
+	cell->setPort("\\Q", sig_out);
 	if (arst)
-		cell->set("\\ARST", *arst);
-	cell->set("\\CLK", clk);
+		cell->setPort("\\ARST", *arst);
+	cell->setPort("\\CLK", clk);
 
 	log("  created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
 	if (arst)
@@ -295,9 +295,9 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 				cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
 				cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
 				cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
-				cell->set("\\A", inputs);
-				cell->set("\\B", compare);
-				cell->set("\\Y", sync_level->signal);
+				cell->setPort("\\A", inputs);
+				cell->setPort("\\B", compare);
+				cell->setPort("\\Y", sync_level->signal);
 
 				many_async_rules.clear();
 			}
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index b18ce4925..c00b00a2a 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -92,9 +92,9 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 			eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
 			eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
-			eq_cell->set("\\A", sig);
-			eq_cell->set("\\B", comp);
-			eq_cell->set("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
+			eq_cell->setPort("\\A", sig);
+			eq_cell->setPort("\\B", comp);
+			eq_cell->setPort("\\Y", RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
 		}
 	}
 
@@ -115,8 +115,8 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 		any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
 		any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
 
-		any_cell->set("\\A", cmp_wire);
-		any_cell->set("\\Y", RTLIL::SigSpec(ctrl_wire));
+		any_cell->setPort("\\A", cmp_wire);
+		any_cell->setPort("\\Y", RTLIL::SigSpec(ctrl_wire));
 	}
 
 	return RTLIL::SigSpec(ctrl_wire);
@@ -147,10 +147,10 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 	mux_cell->attributes = sw->attributes;
 
 	mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
-	mux_cell->set("\\A", else_signal);
-	mux_cell->set("\\B", when_signal);
-	mux_cell->set("\\S", ctrl_sig);
-	mux_cell->set("\\Y", RTLIL::SigSpec(result_wire));
+	mux_cell->setPort("\\A", else_signal);
+	mux_cell->setPort("\\B", when_signal);
+	mux_cell->setPort("\\S", ctrl_sig);
+	mux_cell->setPort("\\Y", RTLIL::SigSpec(result_wire));
 
 	last_mux_cell = mux_cell;
 	return RTLIL::SigSpec(result_wire);
@@ -159,21 +159,21 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
 {
 	log_assert(last_mux_cell != NULL);
-	log_assert(when_signal.size() == last_mux_cell->get("\\A").size());
+	log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size());
 
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
 	log_assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
 
-	RTLIL::SigSpec new_s = last_mux_cell->get("\\S");
+	RTLIL::SigSpec new_s = last_mux_cell->getPort("\\S");
 	new_s.append(ctrl_sig);
-	last_mux_cell->set("\\S", new_s);
+	last_mux_cell->setPort("\\S", new_s);
 
-	RTLIL::SigSpec new_b = last_mux_cell->get("\\B");
+	RTLIL::SigSpec new_b = last_mux_cell->getPort("\\B");
 	new_b.append(when_signal);
-	last_mux_cell->set("\\B", new_b);
+	last_mux_cell->setPort("\\B", new_b);
 
-	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->get("\\S").size();
+	last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size();
 }
 
 static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval)
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index f2b89b000..25b9e1d11 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -83,8 +83,8 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
 	SigPool dffsignals;
 
 	for (auto &it : module->cells_) {
-		if (ct.cell_known(it.second->type) && it.second->has("\\Q"))
-			dffsignals.add(sigmap(it.second->get("\\Q")));
+		if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q"))
+			dffsignals.add(sigmap(it.second->getPort("\\Q")));
 	}
 
 	for (auto &it : module->wires_) {
@@ -113,10 +113,10 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		info.cell = it.second;
 
 		if (info.cell->type == "$dff") {
-			info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
 			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
-			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
 			for (size_t i = 0; i < sig_d.size(); i++) {
 				info.bit_d = sig_d.at(i);
 				bit_info[sig_q.at(i)] = info;
@@ -125,12 +125,12 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		}
 
 		if (info.cell->type == "$adff") {
-			info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
-			info.bit_arst = sigmap(info.cell->get("\\ARST")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
+			info.bit_arst = sigmap(info.cell->getPort("\\ARST")).to_single_sigbit();
 			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
 			info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
-			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
-			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
+			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
 			std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
 			for (size_t i = 0; i < sig_d.size(); i++) {
 				info.bit_d = sig_d.at(i);
@@ -141,21 +141,21 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		}
 
 		if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
-			info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
 			info.clk_polarity = info.cell->type == "$_DFF_P_";
-			info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
-			bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
+			info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
+			bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
 			continue;
 		}
 
 		if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
-			info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
-			info.bit_arst = sigmap(info.cell->get("\\R")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
+			info.bit_arst = sigmap(info.cell->getPort("\\R")).to_single_sigbit();
 			info.clk_polarity = info.cell->type[6] == 'P';
 			info.arst_polarity = info.cell->type[7] == 'P';
 			info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
-			info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
-			bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
+			info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
+			bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
 			continue;
 		}
 	}
@@ -504,11 +504,11 @@ struct ExposePass : public Pass {
 
 				for (auto &cell_name : info.cells) {
 					RTLIL::Cell *cell = module->cells_.at(cell_name);
-					std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector();
+					std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
 					for (auto &bit : cell_q_bits)
 						if (wire_bits_set.count(bit))
 							bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
-					cell->set("\\Q", cell_q_bits);
+					cell->setPort("\\Q", cell_q_bits);
 				}
 
 				RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width);
@@ -540,8 +540,8 @@ struct ExposePass : public Pass {
 					c->parameters["\\A_SIGNED"] = 0;
 					c->parameters["\\A_WIDTH"] = 1;
 					c->parameters["\\Y_WIDTH"] = 1;
-					c->set("\\A", info.sig_clk);
-					c->set("\\Y", wire_c);
+					c->setPort("\\A", info.sig_clk);
+					c->setPort("\\Y", wire_c);
 				}
 
 				if (info.sig_arst != RTLIL::State::Sm)
@@ -556,8 +556,8 @@ struct ExposePass : public Pass {
 						c->parameters["\\A_SIGNED"] = 0;
 						c->parameters["\\A_WIDTH"] = 1;
 						c->parameters["\\Y_WIDTH"] = 1;
-						c->set("\\A", info.sig_arst);
-						c->set("\\Y", wire_r);
+						c->setPort("\\A", info.sig_arst);
+						c->setPort("\\Y", wire_r);
 					}
 
 					RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width);
@@ -602,8 +602,8 @@ struct ExposePass : public Pass {
 							log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
 							RTLIL::SigSpec sig;
-							if (cell->has(p->name))
-								sig = cell->get(p->name);
+							if (cell->hasPort(p->name))
+								sig = cell->getPort(p->name);
 							sig.extend(w->width);
 							if (w->port_input)
 								module->connect(RTLIL::SigSig(sig, w));
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index ad304c723..7b9fb2072 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -624,7 +624,7 @@ struct FreduceWorker
 				bits_full_total += outputs.size();
 			}
 			if (inv_mode && it.second->type == "$_INV_")
-				inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->get("\\A")), sigmap(it.second->get("\\Y"))));
+				inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
 		}
 
 		int bits_count = 0;
@@ -719,8 +719,8 @@ struct FreduceWorker
 						inv_sig = module->addWire(NEW_ID);
 
 						RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
-						inv_cell->set("\\A", grp[0].bit);
-						inv_cell->set("\\Y", inv_sig);
+						inv_cell->setPort("\\A", grp[0].bit);
+						inv_cell->setPort("\\Y", inv_sig);
 					}
 
 					module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index ffd9f1b62..1475b855e 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -129,8 +129,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width);
 			w2->port_input = true;
 
-			gold_cell->set(w1->name, w2);
-			gate_cell->set(w1->name, w2);
+			gold_cell->setPort(w1->name, w2);
+			gate_cell->setPort(w1->name, w2);
 		}
 
 		if (w1->port_output)
@@ -141,8 +141,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 			RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width);
 			w2_gate->port_output = flag_make_outputs;
 
-			gold_cell->set(w1->name, w2_gold);
-			gate_cell->set(w1->name, w2_gate);
+			gold_cell->setPort(w1->name, w2_gold);
+			gate_cell->setPort(w1->name, w2_gate);
 
 			RTLIL::SigSpec this_condition;
 
@@ -156,9 +156,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 					eqx_cell->parameters["\\Y_WIDTH"] = 1;
 					eqx_cell->parameters["\\A_SIGNED"] = 0;
 					eqx_cell->parameters["\\B_SIGNED"] = 0;
-					eqx_cell->set("\\A", RTLIL::SigSpec(w2_gold, i));
-					eqx_cell->set("\\B", RTLIL::State::Sx);
-					eqx_cell->set("\\Y", gold_x.extract(i, 1));
+					eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i));
+					eqx_cell->setPort("\\B", RTLIL::State::Sx);
+					eqx_cell->setPort("\\Y", gold_x.extract(i, 1));
 				}
 
 				RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
@@ -170,9 +170,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
 				or_gold_cell->parameters["\\A_SIGNED"] = 0;
 				or_gold_cell->parameters["\\B_SIGNED"] = 0;
-				or_gold_cell->set("\\A", w2_gold);
-				or_gold_cell->set("\\B", gold_x);
-				or_gold_cell->set("\\Y", gold_masked);
+				or_gold_cell->setPort("\\A", w2_gold);
+				or_gold_cell->setPort("\\B", gold_x);
+				or_gold_cell->setPort("\\Y", gold_masked);
 
 				RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
 				or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
@@ -180,9 +180,9 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
 				or_gate_cell->parameters["\\A_SIGNED"] = 0;
 				or_gate_cell->parameters["\\B_SIGNED"] = 0;
-				or_gate_cell->set("\\A", w2_gate);
-				or_gate_cell->set("\\B", gold_x);
-				or_gate_cell->set("\\Y", gate_masked);
+				or_gate_cell->setPort("\\A", w2_gate);
+				or_gate_cell->setPort("\\B", gold_x);
+				or_gate_cell->setPort("\\Y", gate_masked);
 
 				RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
 				eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
@@ -190,10 +190,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				eq_cell->parameters["\\Y_WIDTH"] = 1;
 				eq_cell->parameters["\\A_SIGNED"] = 0;
 				eq_cell->parameters["\\B_SIGNED"] = 0;
-				eq_cell->set("\\A", gold_masked);
-				eq_cell->set("\\B", gate_masked);
-				eq_cell->set("\\Y", miter_module->addWire(NEW_ID));
-				this_condition = eq_cell->get("\\Y");
+				eq_cell->setPort("\\A", gold_masked);
+				eq_cell->setPort("\\B", gate_masked);
+				eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
+				this_condition = eq_cell->getPort("\\Y");
 			}
 			else
 			{
@@ -203,10 +203,10 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 				eq_cell->parameters["\\Y_WIDTH"] = 1;
 				eq_cell->parameters["\\A_SIGNED"] = 0;
 				eq_cell->parameters["\\B_SIGNED"] = 0;
-				eq_cell->set("\\A", w2_gold);
-				eq_cell->set("\\B", w2_gate);
-				eq_cell->set("\\Y", miter_module->addWire(NEW_ID));
-				this_condition = eq_cell->get("\\Y");
+				eq_cell->setPort("\\A", w2_gold);
+				eq_cell->setPort("\\B", w2_gate);
+				eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
+				this_condition = eq_cell->getPort("\\Y");
 			}
 
 			if (flag_make_outcmp)
@@ -225,15 +225,15 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 		reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 		reduce_cell->parameters["\\Y_WIDTH"] = 1;
 		reduce_cell->parameters["\\A_SIGNED"] = 0;
-		reduce_cell->set("\\A", all_conditions);
-		reduce_cell->set("\\Y", miter_module->addWire(NEW_ID));
-		all_conditions = reduce_cell->get("\\Y");
+		reduce_cell->setPort("\\A", all_conditions);
+		reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
+		all_conditions = reduce_cell->getPort("\\Y");
 	}
 
 	if (flag_make_assert) {
 		RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
-		assert_cell->set("\\A", all_conditions);
-		assert_cell->set("\\EN", RTLIL::SigSpec(1, 1));
+		assert_cell->setPort("\\A", all_conditions);
+		assert_cell->setPort("\\EN", RTLIL::SigSpec(1, 1));
 	}
 
 	RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger");
@@ -244,8 +244,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
 	not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
 	not_cell->parameters["\\A_SIGNED"] = 0;
-	not_cell->set("\\A", all_conditions);
-	not_cell->set("\\Y", w_trigger);
+	not_cell->setPort("\\A", all_conditions);
+	not_cell->setPort("\\Y", w_trigger);
 
 	miter_module->fixup_ports();
 
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 671a631dd..1041227ed 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -77,7 +77,7 @@ struct ShareWorker
 
 			for (auto &pbit : portbits) {
 				if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") {
-					std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->get("\\S")).to_sigbit_set();
+					std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_set();
 					terminal_bits.insert(bits.begin(), bits.end());
 					queue_bits.insert(bits.begin(), bits.end());
 					visited_cells.insert(pbit.cell);
@@ -256,11 +256,11 @@ struct ShareWorker
 			if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
 			{
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
-				if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
+				if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
-					RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
+					RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A");
 					new_a.append_bit(RTLIL::State::S0);
-					unsigned_cell->set("\\A", new_a);
+					unsigned_cell->setPort("\\A", new_a);
 				}
 				unsigned_cell->parameters.at("\\A_SIGNED") = true;
 				unsigned_cell->check();
@@ -269,17 +269,17 @@ struct ShareWorker
 			bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
 			log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool());
 
-			RTLIL::SigSpec a1 = c1->get("\\A");
-			RTLIL::SigSpec y1 = c1->get("\\Y");
+			RTLIL::SigSpec a1 = c1->getPort("\\A");
+			RTLIL::SigSpec y1 = c1->getPort("\\Y");
 
-			RTLIL::SigSpec a2 = c2->get("\\A");
-			RTLIL::SigSpec y2 = c2->get("\\Y");
+			RTLIL::SigSpec a2 = c2->getPort("\\A");
+			RTLIL::SigSpec y2 = c2->getPort("\\Y");
 
 			int a_width = std::max(a1.size(), a2.size());
 			int y_width = std::max(y1.size(), y2.size());
 
-			if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
-			if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
+			if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y");
+			if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y");
 
 			RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
 			RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
@@ -288,8 +288,8 @@ struct ShareWorker
 			supercell->parameters["\\A_SIGNED"] = a_signed;
 			supercell->parameters["\\A_WIDTH"] = a_width;
 			supercell->parameters["\\Y_WIDTH"] = y_width;
-			supercell->set("\\A", a);
-			supercell->set("\\Y", y);
+			supercell->setPort("\\A", a);
+			supercell->setPort("\\Y", y);
 
 			RTLIL::SigSpec new_y1(y, 0, y1.size());
 			RTLIL::SigSpec new_y2(y, 0, y2.size());
@@ -314,9 +314,9 @@ struct ShareWorker
 
 				if (score_flipped < score_unflipped)
 				{
-					RTLIL::SigSpec tmp = c2->get("\\A");
-					c2->set("\\A", c2->get("\\B"));
-					c2->set("\\B", tmp);
+					RTLIL::SigSpec tmp = c2->getPort("\\A");
+					c2->setPort("\\A", c2->getPort("\\B"));
+					c2->setPort("\\B", tmp);
 
 					std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH"));
 					std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED"));
@@ -328,11 +328,11 @@ struct ShareWorker
 
 			{
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
-				if (unsigned_cell->get("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
+				if (unsigned_cell->getPort("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
-					RTLIL::SigSpec new_a = unsigned_cell->get("\\A");
+					RTLIL::SigSpec new_a = unsigned_cell->getPort("\\A");
 					new_a.append_bit(RTLIL::State::S0);
-					unsigned_cell->set("\\A", new_a);
+					unsigned_cell->setPort("\\A", new_a);
 				}
 				unsigned_cell->parameters.at("\\A_SIGNED") = true;
 				modified_src_cells = true;
@@ -341,11 +341,11 @@ struct ShareWorker
 			if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
 			{
 				RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1;
-				if (unsigned_cell->get("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
+				if (unsigned_cell->getPort("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
 					unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1;
-					RTLIL::SigSpec new_b = unsigned_cell->get("\\B");
+					RTLIL::SigSpec new_b = unsigned_cell->getPort("\\B");
 					new_b.append_bit(RTLIL::State::S0);
-					unsigned_cell->set("\\B", new_b);
+					unsigned_cell->setPort("\\B", new_b);
 				}
 				unsigned_cell->parameters.at("\\B_SIGNED") = true;
 				modified_src_cells = true;
@@ -365,13 +365,13 @@ struct ShareWorker
 			if (c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
 				b_signed = false;
 
-			RTLIL::SigSpec a1 = c1->get("\\A");
-			RTLIL::SigSpec b1 = c1->get("\\B");
-			RTLIL::SigSpec y1 = c1->get("\\Y");
+			RTLIL::SigSpec a1 = c1->getPort("\\A");
+			RTLIL::SigSpec b1 = c1->getPort("\\B");
+			RTLIL::SigSpec y1 = c1->getPort("\\Y");
 
-			RTLIL::SigSpec a2 = c2->get("\\A");
-			RTLIL::SigSpec b2 = c2->get("\\B");
-			RTLIL::SigSpec y2 = c2->get("\\Y");
+			RTLIL::SigSpec a2 = c2->getPort("\\A");
+			RTLIL::SigSpec b2 = c2->getPort("\\B");
+			RTLIL::SigSpec y2 = c2->getPort("\\Y");
 
 			int a_width = std::max(a1.size(), a2.size());
 			int b_width = std::max(b1.size(), b2.size());
@@ -381,20 +381,20 @@ struct ShareWorker
 			{
 				a_width = std::max(y_width, a_width);
 
-				if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->get("\\Y");
-				if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->get("\\Y");
+				if (a1.size() < y1.size()) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, y1.size()), true)->getPort("\\Y");
+				if (a2.size() < y2.size()) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, y2.size()), true)->getPort("\\Y");
 
-				if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->get("\\Y");
-				if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->get("\\Y");
+				if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), false)->getPort("\\Y");
+				if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), false)->getPort("\\Y");
 			}
 			else
 			{
-				if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
-				if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->get("\\Y");
+				if (a1.size() != a_width) a1 = module->addPos(NEW_ID, a1, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y");
+				if (a2.size() != a_width) a2 = module->addPos(NEW_ID, a2, module->addWire(NEW_ID, a_width), a_signed)->getPort("\\Y");
 			}
 
-			if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y");
-			if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->get("\\Y");
+			if (b1.size() != b_width) b1 = module->addPos(NEW_ID, b1, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y");
+			if (b2.size() != b_width) b2 = module->addPos(NEW_ID, b2, module->addWire(NEW_ID, b_width), b_signed)->getPort("\\Y");
 
 			RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
 			RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act);
@@ -406,9 +406,9 @@ struct ShareWorker
 			supercell->parameters["\\A_WIDTH"] = a_width;
 			supercell->parameters["\\B_WIDTH"] = b_width;
 			supercell->parameters["\\Y_WIDTH"] = y_width;
-			supercell->set("\\A", a);
-			supercell->set("\\B", b);
-			supercell->set("\\Y", y);
+			supercell->setPort("\\A", a);
+			supercell->setPort("\\B", b);
+			supercell->setPort("\\Y", y);
 			supercell->check();
 
 			RTLIL::SigSpec new_y1(y, 0, y1.size());
@@ -447,7 +447,7 @@ struct ShareWorker
 
 		for (auto &bit : pbits) {
 			if ((bit.cell->type == "$mux" || bit.cell->type == "$pmux") && bit.port == "\\S")
-				forbidden_controls_cache[cell].insert(bit.cell->get("\\S").extract(bit.offset, 1));
+				forbidden_controls_cache[cell].insert(bit.cell->getPort("\\S").extract(bit.offset, 1));
 			consumer_cells.insert(bit.cell);
 		}
 
@@ -541,9 +541,9 @@ struct ShareWorker
 			std::set<int> used_in_b_parts;
 
 			int width = c->parameters.at("\\WIDTH").as_int();
-			std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->get("\\A"));
-			std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->get("\\B"));
-			std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->get("\\S"));
+			std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort("\\A"));
+			std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort("\\B"));
+			std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort("\\S"));
 
 			for (auto &bit : sig_a)
 				if (cell_out_bits.count(bit))
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index ffe241182..7712d18b9 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 			} else
 			if (port.second != 0)
 				log_abort();
-			new_cell->set("\\" + port.first, sig);
+			new_cell->setPort("\\" + port.first, sig);
 		}
 
 		stats[stringf("  mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 060a87407..53bc00daf 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -127,7 +127,7 @@ namespace
 				for (auto &conn : needleCell->connections())
 				{
 					RTLIL::SigSpec needleSig = conn.second;
-					RTLIL::SigSpec haystackSig = haystackCell->get(portMapping.at(conn.first));
+					RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first));
 
 					for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
 						RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@@ -304,7 +304,7 @@ namespace
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
 					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
-				cell->set(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
+				cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
 			}
 		}
 
@@ -323,10 +323,10 @@ namespace
 				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
 					for (int i = 0; i < sig.size(); i++)
 					for (auto &port : sig2port.find(sig[i])) {
-						RTLIL::SigSpec bitsig = haystack_cell->get(mapping.portMapping[conn.first]).extract(i, 1);
-						RTLIL::SigSpec new_sig = cell->get(port.first);
+						RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first]).extract(i, 1);
+						RTLIL::SigSpec new_sig = cell->getPort(port.first);
 						new_sig.replace(port.second, bitsig);
-						cell->set(port.first, new_sig);
+						cell->setPort(port.first, new_sig);
 					}
 				}
 			}
@@ -742,7 +742,7 @@ struct ExtractPass : public Pass {
 						for (auto &chunk : chunks)
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires_.at(chunk.wire->name);
-						newCell->set(conn.first, chunks);
+						newCell->setPort(conn.first, chunks);
 					}
 				}
 			}
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index a3261dccd..784c4cf31 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
 				last_hi = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
-				cell->set(RTLIL::escape_id(hicell_portname), last_hi);
+				cell->setPort(RTLIL::escape_id(hicell_portname), last_hi);
 			}
 			bit = last_hi;
 		}
@@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
 				last_lo = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
-				cell->set(RTLIL::escape_id(locell_portname), last_lo);
+				cell->setPort(RTLIL::escape_id(locell_portname), last_lo);
 			}
 			bit = last_lo;
 		}
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 10627cd12..194e06a4a 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -172,9 +172,9 @@ struct IopadmapPass : public Pass {
 					for (int i = 0; i < wire->width; i++)
 					{
 						RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-						cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
+						cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
 						if (!portname2.empty())
-							cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
+							cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
 						if (!widthparam.empty())
 							cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
 						if (!nameparam.empty())
@@ -185,9 +185,9 @@ struct IopadmapPass : public Pass {
 				else
 				{
 					RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-					cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
+					cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
 					if (!portname2.empty())
-						cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
+						cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
 					if (!widthparam.empty())
 						cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
 					if (!nameparam.empty())
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 5c3e4c68f..f1f334f6e 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -28,22 +28,22 @@ extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*,
 
 static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-		gate->set("\\A", sig_a[i]);
-		gate->set("\\Y", sig_y[i]);
+		gate->setPort("\\A", sig_a[i]);
+		gate->setPort("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 	sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
@@ -52,8 +52,8 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
 
 static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 	sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 
@@ -62,9 +62,9 @@ static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
 
 static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_b = cell->get("\\B");
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
+	RTLIL::SigSpec sig_b = cell->getPort("\\B");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 	sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
 	sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
@@ -75,8 +75,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 
 		for (int i = 0; i < SIZE(sig_y); i++) {
 			RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-			gate->set("\\A", sig_t[i]);
-			gate->set("\\Y", sig_y[i]);
+			gate->setPort("\\A", sig_t[i]);
+			gate->setPort("\\Y", sig_y[i]);
 		}
 
 		sig_y = sig_t;
@@ -91,16 +91,16 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->set("\\A", sig_a[i]);
-		gate->set("\\B", sig_b[i]);
-		gate->set("\\Y", sig_y[i]);
+		gate->setPort("\\A", sig_a[i]);
+		gate->setPort("\\B", sig_b[i]);
+		gate->setPort("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
@@ -141,9 +141,9 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-			gate->set("\\A", sig_a[i]);
-			gate->set("\\B", sig_a[i+1]);
-			gate->set("\\Y", sig_t[i/2]);
+			gate->setPort("\\A", sig_a[i]);
+			gate->setPort("\\B", sig_a[i+1]);
+			gate->setPort("\\Y", sig_t[i/2]);
 			last_output_cell = gate;
 		}
 
@@ -153,8 +153,8 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == "$reduce_xnor") {
 		RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-		gate->set("\\A", sig_a);
-		gate->set("\\Y", sig_t);
+		gate->setPort("\\A", sig_a);
+		gate->setPort("\\Y", sig_t);
 		last_output_cell = gate;
 		sig_a = sig_t;
 	}
@@ -162,7 +162,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (last_output_cell == NULL) {
 		module->connect(RTLIL::SigSig(sig_y, sig_a));
 	} else {
-		last_output_cell->set("\\Y", sig_y);
+		last_output_cell->setPort("\\Y", sig_y);
 	}
 }
 
@@ -180,9 +180,9 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 			}
 
 			RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
-			gate->set("\\A", sig[i]);
-			gate->set("\\B", sig[i+1]);
-			gate->set("\\Y", sig_t[i/2]);
+			gate->setPort("\\A", sig[i]);
+			gate->setPort("\\B", sig[i+1]);
+			gate->setPort("\\Y", sig_t[i/2]);
 		}
 
 		sig = sig_t;
@@ -194,10 +194,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
 
 static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
 	logic_reduce(module, sig_a);
 
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
@@ -208,19 +208,19 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
-	gate->set("\\A", sig_a);
-	gate->set("\\Y", sig_y);
+	gate->setPort("\\A", sig_a);
+	gate->setPort("\\Y", sig_y);
 }
 
 static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->get("\\A");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
 	logic_reduce(module, sig_a);
 
-	RTLIL::SigSpec sig_b = cell->get("\\B");
+	RTLIL::SigSpec sig_b = cell->getPort("\\B");
 	logic_reduce(module, sig_b);
 
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 	if (sig_y.size() == 0)
 		return;
@@ -236,39 +236,39 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
 	log_assert(!gate_type.empty());
 
 	RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-	gate->set("\\A", sig_a);
-	gate->set("\\B", sig_b);
-	gate->set("\\Y", sig_y);
+	gate->setPort("\\A", sig_a);
+	gate->setPort("\\B", sig_b);
+	gate->setPort("\\Y", sig_y);
 }
 
 static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_b = cell->get("\\B");
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
+	RTLIL::SigSpec sig_b = cell->getPort("\\B");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 
 	for (int i = 0; i < SIZE(sig_y); i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
-		gate->set("\\A", sig_a[i]);
-		gate->set("\\B", sig_b[i]);
-		gate->set("\\S", cell->get("\\S"));
-		gate->set("\\Y", sig_y[i]);
+		gate->setPort("\\A", sig_a[i]);
+		gate->setPort("\\B", sig_b[i]);
+		gate->setPort("\\S", cell->getPort("\\S"));
+		gate->setPort("\\Y", sig_y[i]);
 	}
 }
 
 static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	int offset = cell->parameters.at("\\OFFSET").as_int();
-	RTLIL::SigSpec sig_a = cell->get("\\A");
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_a = cell->getPort("\\A");
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 	module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
 }
 
 static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
 {
-	RTLIL::SigSpec sig_ab = cell->get("\\A");
-	sig_ab.append(cell->get("\\B"));
-	RTLIL::SigSpec sig_y = cell->get("\\Y");
+	RTLIL::SigSpec sig_ab = cell->getPort("\\A");
+	sig_ab.append(cell->getPort("\\B"));
+	RTLIL::SigSpec sig_y = cell->getPort("\\Y");
 	module->connect(RTLIL::SigSig(sig_y, sig_ab));
 }
 
@@ -278,17 +278,17 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
 	char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 	char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_s = cell->get("\\SET");
-	RTLIL::SigSpec sig_r = cell->get("\\CLR");
-	RTLIL::SigSpec sig_q = cell->get("\\Q");
+	RTLIL::SigSpec sig_s = cell->getPort("\\SET");
+	RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
+	RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 
 	std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->set("\\S", sig_s[i]);
-		gate->set("\\R", sig_r[i]);
-		gate->set("\\Q", sig_q[i]);
+		gate->setPort("\\S", sig_s[i]);
+		gate->setPort("\\R", sig_r[i]);
+		gate->setPort("\\Q", sig_q[i]);
 	}
 }
 
@@ -297,17 +297,17 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
 	int width = cell->parameters.at("\\WIDTH").as_int();
 	char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
-	RTLIL::SigSpec sig_d = cell->get("\\D");
-	RTLIL::SigSpec sig_q = cell->get("\\Q");
+	RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
+	RTLIL::SigSpec sig_d = cell->getPort("\\D");
+	RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 
 	std::string gate_type = stringf("$_DFF_%c_", clk_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->set("\\C", sig_clk);
-		gate->set("\\D", sig_d[i]);
-		gate->set("\\Q", sig_q[i]);
+		gate->setPort("\\C", sig_clk);
+		gate->setPort("\\D", sig_d[i]);
+		gate->setPort("\\Q", sig_q[i]);
 	}
 }
 
@@ -318,21 +318,21 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
 	char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
 	char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
-	RTLIL::SigSpec sig_s = cell->get("\\SET");
-	RTLIL::SigSpec sig_r = cell->get("\\CLR");
-	RTLIL::SigSpec sig_d = cell->get("\\D");
-	RTLIL::SigSpec sig_q = cell->get("\\Q");
+	RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
+	RTLIL::SigSpec sig_s = cell->getPort("\\SET");
+	RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
+	RTLIL::SigSpec sig_d = cell->getPort("\\D");
+	RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 
 	std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->set("\\C", sig_clk);
-		gate->set("\\S", sig_s[i]);
-		gate->set("\\R", sig_r[i]);
-		gate->set("\\D", sig_d[i]);
-		gate->set("\\Q", sig_q[i]);
+		gate->setPort("\\C", sig_clk);
+		gate->setPort("\\S", sig_s[i]);
+		gate->setPort("\\R", sig_r[i]);
+		gate->setPort("\\D", sig_d[i]);
+		gate->setPort("\\Q", sig_q[i]);
 	}
 }
 
@@ -346,20 +346,20 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
 	while (int(rst_val.size()) < width)
 		rst_val.push_back(RTLIL::State::S0);
 
-	RTLIL::SigSpec sig_clk = cell->get("\\CLK");
-	RTLIL::SigSpec sig_rst = cell->get("\\ARST");
-	RTLIL::SigSpec sig_d = cell->get("\\D");
-	RTLIL::SigSpec sig_q = cell->get("\\Q");
+	RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
+	RTLIL::SigSpec sig_rst = cell->getPort("\\ARST");
+	RTLIL::SigSpec sig_d = cell->getPort("\\D");
+	RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 
 	std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
 	std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
-		gate->set("\\C", sig_clk);
-		gate->set("\\R", sig_rst);
-		gate->set("\\D", sig_d[i]);
-		gate->set("\\Q", sig_q[i]);
+		gate->setPort("\\C", sig_clk);
+		gate->setPort("\\R", sig_rst);
+		gate->setPort("\\D", sig_d[i]);
+		gate->setPort("\\Q", sig_q[i]);
 	}
 }
 
@@ -368,17 +368,17 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 	int width = cell->parameters.at("\\WIDTH").as_int();
 	char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
 
-	RTLIL::SigSpec sig_en = cell->get("\\EN");
-	RTLIL::SigSpec sig_d = cell->get("\\D");
-	RTLIL::SigSpec sig_q = cell->get("\\Q");
+	RTLIL::SigSpec sig_en = cell->getPort("\\EN");
+	RTLIL::SigSpec sig_d = cell->getPort("\\D");
+	RTLIL::SigSpec sig_q = cell->getPort("\\Q");
 
 	std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
 
 	for (int i = 0; i < width; i++) {
 		RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
-		gate->set("\\E", sig_en);
-		gate->set("\\D", sig_d[i]);
-		gate->set("\\Q", sig_q[i]);
+		gate->setPort("\\E", sig_en);
+		gate->setPort("\\D", sig_d[i]);
+		gate->setPort("\\Q", sig_q[i]);
 	}
 }
 
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 4034f120e..946490135 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -38,7 +38,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std
 		RTLIL::Wire *wire = module->addWire("\\A");
 		wire->width = 1 + xorshift32(8);
 		wire->port_input = true;
-		cell->set("\\A", wire);
+		cell->setPort("\\A", wire);
 	}
 
 	if (cell_type_flags.find('B') != std::string::npos) {
@@ -48,7 +48,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std
 		else
 			wire->width = 1 + xorshift32(8);
 		wire->port_input = true;
-		cell->set("\\B", wire);
+		cell->setPort("\\B", wire);
 	}
 
 	if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
@@ -69,7 +69,7 @@ static void create_gold_module(RTLIL::Design *design, std::string cell_type, std
 		RTLIL::Wire *wire = module->addWire("\\Y");
 		wire->width = 1 + xorshift32(8);
 		wire->port_output = true;
-		cell->set("\\Y", wire);
+		cell->setPort("\\Y", wire);
 	}
 
 	module->fixup_ports();