| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | * | | | memory_collect: Copy attr from RTLIL::Memory to cell | David Shah | 2019-11-18 | 1 | -0/+4 | |
| * | | | | Merge pull request #1534 from YosysHQ/mwk/opt_share-fix | Clifford Wolf | 2019-11-27 | 2 | -4/+24 | |
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| | * | | | | opt_share: Fix handling of fine cells. | Marcin Kościelnicki | 2019-11-27 | 2 | -4/+24 | |
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| * | | | | Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve | Eddie Hung | 2019-11-27 | 2 | -22/+5 | |
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| | * | | | latch -> box | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
| | * | | | Remove notes | Eddie Hung | 2019-11-26 | 1 | -9/+0 | |
| | * | | | Fold loop | Eddie Hung | 2019-11-26 | 1 | -6/+3 | |
| | * | | | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
| | * | | | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 | |
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| * | | | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 | |
| * | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 4 | -6/+69 | |
| * | | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 5 | -10/+14 | |
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| * | | Merge pull request #1520 from pietrmar/fix-1463 | Eddie Hung | 2019-11-22 | 1 | -2/+0 | |
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| | * | | coolrunner2: remove spurious log_pop() call, fixes #1463 | Martin Pietryka | 2019-11-23 | 1 | -2/+0 | |
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| * | | Merge pull request #1517 from YosysHQ/clifford/optmem | Clifford Wolf | 2019-11-22 | 3 | -0/+146 | |
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| | * | | Add "opt_mem" pass | Clifford Wolf | 2019-11-22 | 3 | -0/+146 | |
| * | | | Merge pull request #1515 from YosysHQ/clifford/svastuff | Clifford Wolf | 2019-11-22 | 2 | -7/+39 | |
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| | * | | Add Verific support for SVA nexttime properties | Clifford Wolf | 2019-11-22 | 1 | -0/+22 | |
| | * | | Improve handling of verific primitives in "verific -import -V" mode | Clifford Wolf | 2019-11-22 | 1 | -2/+2 | |
| | * | | Add Verific SVA support for "always" properties | Clifford Wolf | 2019-11-22 | 1 | -5/+15 | |
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| * | | Merge pull request #1511 from YosysHQ/dave/always | Clifford Wolf | 2019-11-22 | 6 | -9/+126 | |
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| | * | | Update CHANGELOG and README | David Shah | 2019-11-22 | 2 | -0/+7 | |
| | * | | sv: Add tests for SV always types | David Shah | 2019-11-21 | 1 | -0/+63 | |
| | * | | proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage | David Shah | 2019-11-21 | 1 | -4/+16 | |
| | * | | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 2 | -5/+40 | |
| * | | | gowin: Remove show command from tests. | Marcin Kościelnicki | 2019-11-22 | 1 | -1/+0 | |
| * | | | gowin: Add missing .gitignore entries | Marcin Kościelnicki | 2019-11-22 | 1 | -0/+2 | |
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| * | | Merge pull request #1507 from YosysHQ/clifford/verificfixes | Clifford Wolf | 2019-11-20 | 2 | -6/+9 | |
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| | * | | Correctly treat empty modules as blackboxes in Verific | Clifford Wolf | 2019-11-20 | 1 | -1/+1 | |
| | * | | Do not rename VHDL entities to "entity(impl)" when they are top modules | Clifford Wolf | 2019-11-20 | 2 | -5/+8 | |
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| * | | Merge pull request #1449 from pepijndevos/gowin | Clifford Wolf | 2019-11-19 | 27 | -89/+841 | |
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| | * | | Remove dff init altogether | Pepijn de Vos | 2019-11-19 | 2 | -3/+3 | |
| | * | | add help for nowidelut and abc9 options | Pepijn de Vos | 2019-11-18 | 1 | -1/+7 | |
| | * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-16 | 15 | -47/+913 | |
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| | * | | | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 2 | -4/+15 | |
| | * | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-11 | 29 | -23010/+30701 | |
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| | * | | | | fix wide luts | Pepijn de Vos | 2019-11-06 | 2 | -19/+22 | |
| | * | | | | don't cound exact luts in big muxes; futile and fragile | Pepijn de Vos | 2019-10-30 | 1 | -3/+0 | |
| | * | | | | add IOBUF | Pepijn de Vos | 2019-10-28 | 2 | -1/+10 | |
| | * | | | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 3 | -2/+21 | |
| | * | | | | do not use wide luts in testcase | Pepijn de Vos | 2019-10-28 | 1 | -3/+3 | |
| | * | | | | actually run the gowin tests | Pepijn de Vos | 2019-10-28 | 1 | -0/+1 | |
| | * | | | | More formatting | Pepijn de Vos | 2019-10-28 | 1 | -55/+49 | |
| | * | | | | really really fix formatting maybe | Pepijn de Vos | 2019-10-28 | 1 | -41/+41 | |
| | * | | | | undo formatting fuckup | Pepijn de Vos | 2019-10-28 | 1 | -25/+25 | |
| | * | | | | add wide luts | Pepijn de Vos | 2019-10-28 | 3 | -36/+119 | |
| | * | | | | add 32-bit BRAM and byte-enables | Pepijn de Vos | 2019-10-28 | 2 | -4/+25 | |
| | * | | | | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 2 | -13/+13 | |
| | * | | | | Add some tests | Pepijn de Vos | 2019-10-21 | 10 | -0/+224 | |
| | * | | | | add a few more missing dff | Pepijn de Vos | 2019-10-21 | 1 | -7/+16 | |
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