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| -rw-r--r-- | README.md | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -333,7 +333,8 @@ Verilog Attributes and non-standard features is run in ``-pwires`` mode). - Wires marked with the ``hierconn`` attribute are connected to wires with the - same name when they are imported from sub-modules by ``flatten``. + same name (format ``cell_name.identifier``) when they are imported from + sub-modules by ``flatten``. - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` |