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| author | Clifford Wolf <clifford@clifford.at> | 2019-09-05 17:20:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-09-05 17:20:29 +0200 |
| commit | 71d355560e718147ac9ab769363c6a2b069fd209 (patch) | |
| tree | ee5fd48c587aedf4e0b41c24d153b3608e984128 | |
| parent | 30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306 (diff) | |
| download | yosys-71d355560e718147ac9ab769363c6a2b069fd209.tar.gz yosys-71d355560e718147ac9ab769363c6a2b069fd209.tar.bz2 yosys-71d355560e718147ac9ab769363c6a2b069fd209.zip | |
Update README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
| -rw-r--r-- | README.md | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -333,7 +333,8 @@ Verilog Attributes and non-standard features is run in ``-pwires`` mode). - Wires marked with the ``hierconn`` attribute are connected to wires with the - same name when they are imported from sub-modules by ``flatten``. + same name (format ``cell_name.identifier``) when they are imported from + sub-modules by ``flatten``. - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` |