diff options
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 | ||||
| -rw-r--r-- | tests/techmap/bug2759.ys | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index c3eaa70d1..a2f1dd955 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -812,7 +812,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) auto &holes_cell = r.first->second; if (r.second) { if (box_module->get_bool_attribute(ID::whitebox)) { - holes_cell = holes_module->addCell(cell->name, cell->type); + holes_cell = holes_module->addCell(NEW_ID, cell->type); if (box_module->has_processes()) Pass::call_on_module(design, box_module, "proc"); diff --git a/tests/techmap/bug2759.ys b/tests/techmap/bug2759.ys new file mode 100644 index 000000000..05699bef8 --- /dev/null +++ b/tests/techmap/bug2759.ys @@ -0,0 +1,14 @@ +read_verilog -specify <<EOT +(* abc9_box, whitebox *) +module box(input [1:0] i, output o); +specify +(i *> o) = 1; +endspecify +assign o = ^i; +endmodule + +module top(input [1:0] i, output o); +box i1(i, o); +endmodule +EOT +abc9 -lut 4 |