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-rw-r--r--tests/techmap/bug2759.ys14
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/techmap/bug2759.ys b/tests/techmap/bug2759.ys
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index 000000000..05699bef8
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+++ b/tests/techmap/bug2759.ys
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+read_verilog -specify <<EOT
+(* abc9_box, whitebox *)
+module box(input [1:0] i, output o);
+specify
+(i *> o) = 1;
+endspecify
+assign o = ^i;
+endmodule
+
+module top(input [1:0] i, output o);
+box i1(i, o);
+endmodule
+EOT
+abc9 -lut 4