diff options
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 | ||||
| -rw-r--r-- | tests/simple/generate.v | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4895d0302..d89b2dc88 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -517,6 +517,7 @@ wire_type_token: TOK_GENVAR { astbuf3->type = AST_GENVAR; astbuf3->is_reg = true; + astbuf3->is_signed = true; astbuf3->range_left = 31; astbuf3->range_right = 0; } | diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 3c55682cb..0e353ad9b 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -148,3 +148,14 @@ generate endgenerate assign out = steps[WIDTH].outer[0].val; endmodule + +// ------------------------------------------ + +module gen_test6(output [3:0] o); +generate + genvar i; + for (i = 3; i >= 0; i = i-1) begin + assign o[i] = 1'b0; + end +endgenerate +endmodule |