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authorEddie Hung <eddie@fpgeh.com>2019-06-20 16:08:36 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-20 16:08:36 -0700
commit31b0dee7f3f12c76b721f2fa8e11c722307abb09 (patch)
tree832561b85693c6d0826cb20f71613568e7abd383
parent0e3e647596db296e662348625c28b76215b55bcf (diff)
parentc20adc52638b0f3ba3b1c39e5286ae92e901005d (diff)
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Merge remote-tracking branch 'origin/eddie/fix1118' into xc7mux
-rw-r--r--frontends/verilog/verilog_parser.y1
-rw-r--r--tests/simple/generate.v11
2 files changed, 12 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4895d0302..d89b2dc88 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -517,6 +517,7 @@ wire_type_token:
TOK_GENVAR {
astbuf3->type = AST_GENVAR;
astbuf3->is_reg = true;
+ astbuf3->is_signed = true;
astbuf3->range_left = 31;
astbuf3->range_right = 0;
} |
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 3c55682cb..0e353ad9b 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -148,3 +148,14 @@ generate
endgenerate
assign out = steps[WIDTH].outer[0].val;
endmodule
+
+// ------------------------------------------
+
+module gen_test6(output [3:0] o);
+generate
+ genvar i;
+ for (i = 3; i >= 0; i = i-1) begin
+ assign o[i] = 1'b0;
+ end
+endgenerate
+endmodule