From 0a8eaca322a622610efe5a0d33d1cda83e4afa8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Tue, 8 Feb 2022 03:52:50 +0100 Subject: nexus: Use `memory_libmap` pass. --- tests/arch/nexus/blockram.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests/arch') diff --git a/tests/arch/nexus/blockram.ys b/tests/arch/nexus/blockram.ys index 9540136d5..a85b5141e 100644 --- a/tests/arch/nexus/blockram.ys +++ b/tests/arch/nexus/blockram.ys @@ -3,7 +3,7 @@ design -save read # Check that we use the right dual and single clock variants -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp synth_nexus -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:PDPSC16K @@ -11,7 +11,7 @@ select -assert-none t:PDPSC16K t:INV t:IB t:OB t:VLO t:VHI %% t:* %D design -reset read_verilog blockram_dc.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp_dc +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp_dc synth_nexus -top sync_ram_sdp_dc cd sync_ram_sdp_dc select -assert-count 1 t:PDP16K -- cgit v1.2.3