diff options
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 3 | ||||
| -rw-r--r-- | techlibs/xilinx/lut4_lutrams.txt | 19 | ||||
| -rw-r--r-- | techlibs/xilinx/lut6_lutrams.txt (renamed from techlibs/xilinx/lutrams.txt) | 24 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 | ||||
| -rw-r--r-- | tests/arch/xilinx/lutram.ys | 20 |
5 files changed, 42 insertions, 27 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 7785bf81c..d07bae12a 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -38,7 +38,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut4_lutrams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut6_lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v)) diff --git a/techlibs/xilinx/lut4_lutrams.txt b/techlibs/xilinx/lut4_lutrams.txt new file mode 100644 index 000000000..2b344a9ee --- /dev/null +++ b/techlibs/xilinx/lut4_lutrams.txt @@ -0,0 +1,19 @@ +bram $__XILINX_RAM16X1D + init 1 + abits 4 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + + +match $__XILINX_RAM16X1D + min bits 2 + min wports 1 + make_outreg +endmatch diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lut6_lutrams.txt index faf66bc18..3b3cb81e1 100644 --- a/techlibs/xilinx/lutrams.txt +++ b/techlibs/xilinx/lut6_lutrams.txt @@ -1,17 +1,3 @@ - -bram $__XILINX_RAM16X1D - init 1 - abits 4 - dbits 1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 0 1 - transp 0 0 - clocks 0 1 - clkpol 0 2 -endbram - bram $__XILINX_RAM32X1D init 1 abits 5 @@ -105,16 +91,6 @@ bram $__XILINX_RAM64X1Q endbram -# Disabled for now, pending support for LUT4 arches -# since on LUT6 arches this occupies same area as -# a RAM32X1D -#match $__XILINX_RAM16X1D -# min bits 2 -# min wports 1 -# make_outreg -# or_next_if_better -#endmatch - match $__XILINX_RAM32X1D min bits 3 min wports 1 diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index fe58eb6d3..556f85a20 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -318,7 +318,6 @@ struct SynthXilinxPass : public ScriptPass if (lut_size != 6) { log_warning("Shift register inference not yet supported for family %s.\n", family.c_str()); nosrl = true; - nolutram = true; } if (widemux != 0 && widemux < 2) @@ -518,7 +517,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_lutram", "(skip if '-nolutram')")) { if (!nolutram || help_mode) { - run("memory_bram -rules +/xilinx/lutrams.txt"); + run("memory_bram -rules +/xilinx/lut" + lut_size_s + "_lutrams.txt"); run("techmap -map +/xilinx/lutrams_map.v"); } } diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 3f127a77e..cc7354501 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -135,3 +135,23 @@ select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE select -assert-count 2 t:RAM64M select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM16X1D +select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D |