From 1c9634558747bf5b92a309b6af013a54034c35d3 Mon Sep 17 00:00:00 2001 From: Diego H Date: Fri, 13 Dec 2019 09:33:18 -0600 Subject: Renaming BRAM memory tests for the sake of uniformity --- tests/arch/xilinx/blockram_params.ys | 47 ++++++++++++++++++++++++++++++++++++ tests/arch/xilinx/memory_params.ys | 47 ------------------------------------ 2 files changed, 47 insertions(+), 47 deletions(-) create mode 100644 tests/arch/xilinx/blockram_params.ys delete mode 100644 tests/arch/xilinx/memory_params.ys (limited to 'tests/arch/xilinx') diff --git a/tests/arch/xilinx/blockram_params.ys b/tests/arch/xilinx/blockram_params.ys new file mode 100644 index 000000000..27a94834e --- /dev/null +++ b/tests/arch/xilinx/blockram_params.ys @@ -0,0 +1,47 @@ +## TODO: Not running equivalence checking because BRAM models does not exists +## currently. Checking instance counts instead. +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys deleted file mode 100644 index c1b0ca489..000000000 --- a/tests/arch/xilinx/memory_params.ys +++ /dev/null @@ -1,47 +0,0 @@ -## TODO: Not running equivalence checking because BRAM models does not exists -## currently. Checking instance counts instead. -# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -# Anything memory bits < 1024 -> LUTRAM -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 -select -assert-count 4 t:RAM128X1D - -# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB36E1 - -- cgit v1.2.3