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authorClaire Xen <claire@clairexen.net>2022-02-11 16:03:12 +0100
committerGitHub <noreply@github.com>2022-02-11 16:03:12 +0100
commit49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch)
treed0f20b8def36e551c6735d4fc6033aaa2633fe80 /tests/arch/machxo2
parent90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff)
parente0165188669fcef2c5784c9916683889a2164e5d (diff)
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Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'tests/arch/machxo2')
-rw-r--r--tests/arch/machxo2/mux.ys2
-rw-r--r--tests/arch/machxo2/tribuf.ys4
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys
index 6c8aa857c..7b7e62d4c 100644
--- a/tests/arch/machxo2/mux.ys
+++ b/tests/arch/machxo2/mux.ys
@@ -35,6 +35,6 @@ proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 11 t:LUT4
+select -assert-max 12 t:LUT4
select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys
index 9c00a8bcf..fce342e18 100644
--- a/tests/arch/machxo2/tribuf.ys
+++ b/tests/arch/machxo2/tribuf.ys
@@ -6,5 +6,5 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module
select -assert-count 3 t:FACADE_IO
-select -assert-count 1 t:$not
-select -assert-none t:FACADE_IO t:$not %% t:* %D
+select -assert-count 1 t:LUT4
+select -assert-none t:FACADE_IO t:LUT4 %% t:* %D