Merge branch 'master' into clk2ff-better-names

61 files changed, 1010 insertions, 263 deletions

diff --git a/tests/arch/anlogic/blockram.ys b/tests/arch/anlogic/blockram.ys
new file mode 100644
index 000000000..da23409ba
--- /dev/null
+++ b/tests/arch/anlogic/blockram.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sp
+proc
+memory -nomap
+equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
+memory
+opt -full
+
+design -load postopt
+cd sync_ram_sp
+
+select -assert-count 1 t:EG_PHY_BRAM
+select -assert-none t:EG_PHY_BRAM %% t:* %D
diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys
index 9ebb75443..fe6135c73 100644
--- a/tests/arch/anlogic/lutram.ys
+++ b/tests/arch/anlogic/lutram.ys
@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
+equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -nobram
 memory
 opt -full
 
@@ -13,9 +13,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 design -load postopt
 cd lutram_1w1r
 
-select -assert-count 8  t:AL_MAP_LUT2
-select -assert-count 8  t:AL_MAP_LUT4
-select -assert-count 8   t:AL_MAP_LUT5
-select -assert-count 36 t:AL_MAP_SEQ
+select -assert-count 4 t:AL_MAP_LUT3
+select -assert-count 8 t:AL_MAP_LUT6
+select -assert-count 8 t:AL_MAP_SEQ
 select -assert-count 8  t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM?
-select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
+select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT6 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
index 576bd81a6..966e7c2b8 100644
--- a/tests/arch/common/adffs.v
+++ b/tests/arch/common/adffs.v
@@ -1,7 +1,9 @@
 module adff( input d, clk, clr, output reg q );
+`ifndef NO_INIT
     initial begin
         q = 0;
     end
+`endif
 	  always @( posedge clk, posedge clr )
       if ( clr )
         q <= 1'b0;
@@ -10,9 +12,11 @@ module adff( input d, clk, clr, output reg q );
 endmodule
 
 module adffn( input d, clk, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
 	  always @( posedge clk, negedge clr )
 		  if ( !clr )
 			  q <= 1'b0;
@@ -21,9 +25,11 @@ module adffn( input d, clk, clr, output reg q );
 endmodule
 
 module dffs( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
     always @( posedge clk )
       if ( pre )
         q <= 1'b1;
@@ -32,9 +38,11 @@ module dffs( input d, clk, pre, clr, output reg q );
 endmodule
 
 module ndffnr( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
     always @( negedge clk )
       if ( !clr )
         q <= 1'b0;
diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v
index 9746fd701..1e0a13dc9 100644
--- a/tests/arch/common/counter.v
+++ b/tests/arch/common/counter.v
@@ -1,11 +1,11 @@
-module top ( out, clk, reset );

-    output [7:0] out;

-    input clk, reset;

-    reg [7:0] out;

-

-    always @(posedge clk, posedge reset)

-      if (reset)

-          out <= 8'b0;

-      else

-          out <= out + 1;

-endmodule

+module top ( out, clk, reset );
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+      if (reset)
+          out <= 8'b0;
+      else
+          out <= out + 1;
+endmodule
diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v
index 636252d16..0c607af50 100644
--- a/tests/arch/common/dffs.v
+++ b/tests/arch/common/dffs.v
@@ -4,9 +4,11 @@ module dff ( input d, clk, output reg q );
 endmodule
 
 module dffe( input d, clk, en, output reg q );
+`ifndef NO_INIT
     initial begin
         q = 0;
     end
+`endif
 	  always @( posedge clk )
         if ( en )
               q <= d;
diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v
index 9d3fbb64a..cf1c21a58 100644
--- a/tests/arch/common/fsm.v
+++ b/tests/arch/common/fsm.v
@@ -1,51 +1,51 @@
- module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );

-    input   clock,reset,req_0,req_1;

-    output  gnt_0,gnt_1;

-    wire    clock,reset,req_0,req_1;

-    reg     gnt_0,gnt_1;

-

-    parameter SIZE = 3;

-    parameter IDLE = 3'b001;

-    parameter GNT0 = 3'b010;

-    parameter GNT1 = 3'b100;

-    parameter GNT2 = 3'b101;

-

-    reg [SIZE-1:0] state;

-    reg [SIZE-1:0] next_state;

-

-    always @ (posedge clock)

-        begin : FSM

-          if (reset == 1'b1) begin

-            state <=  #1  IDLE;

-            gnt_0 <= 0;

-            gnt_1 <= 0;

-          end 

-          else

-            case(state)

-              IDLE :  if (req_0 == 1'b1) begin

-                          state <=  #1  GNT0;

-                          gnt_0 <= 1;

-                      end else if (req_1 == 1'b1) begin

-                          gnt_1 <= 1;

-                          state <=  #1  GNT0;

-                      end else begin

-                          state <=  #1  IDLE;

-                      end

-              GNT0 :  if (req_0 == 1'b1) begin

-                          state <=  #1  GNT0;

-                      end else begin

-                          gnt_0 <= 0;

-                          state <=  #1  IDLE;

-                      end

-              GNT1 :  if (req_1 == 1'b1) begin

-                          state <=  #1  GNT2;

-                          gnt_1 <= req_0;

-                      end

-              GNT2 :  if (req_0 == 1'b1) begin

-                          state <=  #1  GNT1;

-                          gnt_1 <= req_1;

-                      end

-              default : state <=  #1  IDLE;

-            endcase

-        end

-endmodule

+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
+    input   clock,reset,req_0,req_1;
+    output  gnt_0,gnt_1;
+    wire    clock,reset,req_0,req_1;
+    reg     gnt_0,gnt_1;
+
+    parameter SIZE = 3;
+    parameter IDLE = 3'b001;
+    parameter GNT0 = 3'b010;
+    parameter GNT1 = 3'b100;
+    parameter GNT2 = 3'b101;
+
+    reg [SIZE-1:0] state;
+    reg [SIZE-1:0] next_state;
+
+    always @ (posedge clock)
+        begin : FSM
+          if (reset == 1'b1) begin
+            state <=  #1  IDLE;
+            gnt_0 <= 0;
+            gnt_1 <= 0;
+          end 
+          else
+            case(state)
+              IDLE :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT0;
+                          gnt_0 <= 1;
+                      end else if (req_1 == 1'b1) begin
+                          gnt_1 <= 1;
+                          state <=  #1  GNT0;
+                      end else begin
+                          state <=  #1  IDLE;
+                      end
+              GNT0 :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT0;
+                      end else begin
+                          gnt_0 <= 0;
+                          state <=  #1  IDLE;
+                      end
+              GNT1 :  if (req_1 == 1'b1) begin
+                          state <=  #1  GNT2;
+                          gnt_1 <= req_0;
+                      end
+              GNT2 :  if (req_0 == 1'b1) begin
+                          state <=  #1  GNT1;
+                          gnt_1 <= req_1;
+                      end
+              default : state <=  #1  IDLE;
+            endcase
+        end
+endmodule
diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v
index cace3b588..06e63c9af 100644
--- a/tests/arch/common/shifter.v
+++ b/tests/arch/common/shifter.v
@@ -1,11 +1,17 @@
-module top(out, clk, in);

-    output [7:0] out;

-    input signed clk, in;

-    reg signed [7:0] out = 0;

-

-    always @(posedge clk)

-	begin

-		out    <= out >> 1;

-		out[7] <= in;

-	end    

-endmodule

+module top(out, clk, in);
+    output [7:0] out;
+    input signed clk, in;
+    reg signed [7:0] out;
+
+`ifndef NO_INIT
+    initial begin
+        out = 0;
+    end
+`endif
+
+    always @(posedge clk)
+	begin
+		out    <= out >> 1;
+		out[7] <= in;
+	end    
+endmodule
diff --git a/tests/arch/ecp5/bug2731.ys b/tests/arch/ecp5/bug2731.ys
new file mode 100644
index 000000000..c609cea3b
--- /dev/null
+++ b/tests/arch/ecp5/bug2731.ys
@@ -0,0 +1,7 @@
+read_verilog -icells <<EOF
+module top(input c, r, input [1:0] d, output reg [1:0] q);
+TRELLIS_FF #(.REGSET("SET")) ff1(.CLK(c), .LSR(r), .DI(d[0]), .Q(q[0]));
+TRELLIS_FF #(.REGSET("SET")) ff2(.CLK(c), .LSR(r), .DI(d[1]), .Q(q[1]));
+endmodule
+EOF
+synth_ecp5 -abc9 -dff
diff --git a/tests/arch/ecp5/lutram.ys b/tests/arch/ecp5/lutram.ys
index e1ae7abd5..9bef37c68 100644
--- a/tests/arch/ecp5/lutram.ys
+++ b/tests/arch/ecp5/lutram.ys
@@ -11,9 +11,9 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite
 
 design -load postopt
 cd lutram_1w1r
-select -assert-count 24 t:L6MUX21
-select -assert-count 71 t:LUT4
-select -assert-count 32 t:PFUMX
+select -assert-count 8 t:L6MUX21
+select -assert-count 36 t:LUT4
+select -assert-count 16 t:PFUMX
 select -assert-count 8 t:TRELLIS_DPR16X4
-select -assert-count 35 t:TRELLIS_FF
+select -assert-count 8 t:TRELLIS_FF
 select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys
index f55bf01d2..44651ba25 100644
--- a/tests/arch/ecp5/memories.ys
+++ b/tests/arch/ecp5/memories.ys
@@ -1,328 +1,379 @@
 # ================================ RAM ================================
 # RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:PDPW16KD
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:PDPW16KD # too inefficient
 select -assert-count 9 t:TRELLIS_DPR16X4
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:PDPW16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "Block_RAM" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:PDPW16KD # any case works
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:PDPW16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
 select -assert-count 180 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
 select -assert-count 180 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 # RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 9 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 13 -set DATA_WIDTH 2 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # too inefficient
 select -assert-count 5 t:TRELLIS_DPR16X4
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "Block_RAM" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD # any case works
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 90 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 90 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 # RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:TRELLIS_DPR16X4
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "distributed" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:TRELLIS_DPR16X4
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
 select -assert-count 68 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
 select -assert-count 68 t:TRELLIS_FF
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "distributed" m:memory
 synth_ecp5 -top sync_ram_sdp -nolutram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested LUTRAM but LUTRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested LUTRAM but LUTRAM is disabled
 
 # ================================ ROM ================================
 # ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:PDPW16KD
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:PDPW16KD # too inefficient
 select -assert-min 18 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:PDPW16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:PDPW16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "logic" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
 select -assert-min 18 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
 select -assert-min 18 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_rom" m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
 # ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:DP16KD
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # too inefficient
 select -assert-min 9 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:DP16KD
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "logic" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 9 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set logic_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 9 t:LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set ram_block 1 m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_rom" m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ecp5 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 92463aa32..db63dda5f 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -15,9 +15,9 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:L6MUX21
-select -assert-count 4 t:LUT4
-select -assert-count 2 t:PFUMX
+select -assert-max 1 t:L6MUX21
+select -assert-max 4 t:LUT4
+select -assert-max 2 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
 
@@ -27,9 +27,9 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:L6MUX21
-select -assert-count 7 t:LUT4
-select -assert-count 2 t:PFUMX
+select -assert-max 1 t:L6MUX21
+select -assert-max 7 t:LUT4
+select -assert-max 2 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
 
@@ -39,8 +39,8 @@ proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 8 t:L6MUX21
-select -assert-count 26 t:LUT4
-select -assert-count 12 t:PFUMX
+select -assert-max 12 t:L6MUX21
+select -assert-max 34 t:LUT4
+select -assert-max 17 t:PFUMX
 
 select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
diff --git a/tests/arch/gatemate/.gitignore b/tests/arch/gatemate/.gitignore
new file mode 100644
index 000000000..9a71dca69
--- /dev/null
+++ b/tests/arch/gatemate/.gitignore
@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
++*_synth.v
++*_testbench
diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys
new file mode 100644
index 000000000..bf261ba5a
--- /dev/null
+++ b/tests/arch/gatemate/add_sub.ys
@@ -0,0 +1,9 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:CC_ADDF
+select -assert-max 4 t:CC_LUT1
+select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D
diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys
new file mode 100644
index 000000000..b2ded6e9d
--- /dev/null
+++ b/tests/arch/gatemate/adffs.ys
@@ -0,0 +1,43 @@
+read_verilog -D NO_INIT ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-max 1 t:CC_LUT2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-max 1 t:CC_LUT2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
diff --git a/tests/arch/gatemate/counter.ys b/tests/arch/gatemate/counter.ys
new file mode 100644
index 000000000..77ed858b3
--- /dev/null
+++ b/tests/arch/gatemate/counter.ys
@@ -0,0 +1,12 @@
+read_verilog ../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8 t:CC_ADDF
+select -assert-count 1 t:CC_BUFG
+select -assert-count 8 t:CC_DFF
+select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/dffs.ys b/tests/arch/gatemate/dffs.ys
new file mode 100644
index 000000000..022322419
--- /dev/null
+++ b/tests/arch/gatemate/dffs.ys
@@ -0,0 +1,21 @@
+read_verilog -D NO_INIT ../common/dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys
new file mode 100644
index 000000000..6b43ead7a
--- /dev/null
+++ b/tests/arch/gatemate/fsm.ys
@@ -0,0 +1,20 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+stat
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:CC_BUFG
+select -assert-count 6 t:CC_DFF
+select -assert-max 5 t:CC_LUT2
+select -assert-max 4 t:CC_LUT3
+select -assert-max 9 t:CC_LUT4
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D
diff --git a/tests/arch/gatemate/latches.ys b/tests/arch/gatemate/latches.ys
new file mode 100644
index 000000000..5f64c6db5
--- /dev/null
+++ b/tests/arch/gatemate/latches.ys
@@ -0,0 +1,29 @@
+read_verilog ../common/latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_DLT
+select -assert-none t:CC_DLT %% t:* %D
+
+design -load read
+hierarchy -top latchn
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_DLT
+select -assert-none t:CC_DLT %% t:* %D
+
+design -load read
+hierarchy -top latchsr
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_DLT
+select -assert-max 2 t:CC_LUT3
+select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D
diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys
new file mode 100644
index 000000000..026406bc8
--- /dev/null
+++ b/tests/arch/gatemate/logic.ys
@@ -0,0 +1,10 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-max 1 t:CC_LUT1
+select -assert-max 6 t:CC_LUT2
+select -assert-max 2 t:CC_LUT4
+select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D
diff --git a/tests/arch/gatemate/memory.ys b/tests/arch/gatemate/memory.ys
new file mode 100644
index 000000000..e919920f8
--- /dev/null
+++ b/tests/arch/gatemate/memory.ys
@@ -0,0 +1,34 @@
+# 512 x 40 bit -> CC_BRAM_20K SDP RAM
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_ram_sdp
+synth_gatemate -top sync_ram_sdp -noiopad
+cd sync_ram_sdp
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_BRAM_20K
+
+# 512 x 80 bit -> CC_BRAM_40K SDP RAM
+design -reset
+read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_ram_sdp
+synth_gatemate -top sync_ram_sdp -noiopad
+cd sync_ram_sdp
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_BRAM_40K
+
+# 512 x 40 bit -> CC_BRAM_20K SDP ROM
+design -reset
+read_verilog ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_rom
+synth_gatemate -top sync_rom -noiopad
+cd sync_rom
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_BRAM_20K
+
+# 512 x 80 bit -> CC_BRAM_40K SDP ROM
+design -reset
+read_verilog ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_rom
+synth_gatemate -top sync_rom -noiopad
+cd sync_rom
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_BRAM_40K
diff --git a/tests/arch/gatemate/mul.v b/tests/arch/gatemate/mul.v
new file mode 100644
index 000000000..55e8f9006
--- /dev/null
+++ b/tests/arch/gatemate/mul.v
@@ -0,0 +1,79 @@
+
+module mul_plain(a, b, p);
+
+    parameter M = 6;
+    parameter N = 6;
+
+    input wire [M-1:0] a;
+    input wire [N-1:0] b;
+    output wire [M+N-1:0] p;
+
+    assign p = a * b;
+
+endmodule
+
+module mul_signed_async (clk, rst, en, a, b, p);
+
+    parameter M = 8;
+    parameter N = 6;
+
+    input wire signed clk, rst, en;
+    input wire signed [M-1:0] a;
+    input wire signed [N-1:0] b;
+    output reg signed [M+N-1:0] p;
+
+    reg signed [M-1:0] a_reg;
+    reg signed [N-1:0] b_reg;
+
+    // signed M*N multiplier with
+    // - input and output pipeline registers
+    // - asynchronous reset (active high)
+    // - clock enable (active high)
+    always @(posedge clk or posedge rst)
+    begin
+        if (rst) begin
+            a_reg <= 0;
+            b_reg <= 0;
+            p <= 0;
+        end
+        else if (en) begin
+            a_reg <= a;
+            b_reg <= b;
+            p <= a_reg * b_reg;
+        end
+    end
+
+endmodule
+
+module mul_unsigned_sync (clk, rst, en, a, b, p);
+
+    parameter M = 6;
+    parameter N = 3;
+
+    input wire clk, rst, en;
+    input wire [M-1:0] a;
+    input wire [N-1:0] b;
+    output reg [M+N-1:0] p;
+
+    reg [M-1:0] a_reg;
+    reg [N-1:0] b_reg;
+
+    // unsigned M*N multiplier with
+    // - input and output pipeline registers
+    // - synchronous reset (active high)
+    // - clock enable (active high)
+    always @(posedge clk)
+    begin
+        if (rst) begin
+            a_reg <= 0;
+            b_reg <= 0;
+            p <= 0;
+        end
+        else if (en) begin
+            a_reg <= a;
+            b_reg <= b;
+            p <= a_reg * b_reg;
+        end
+    end
+
+endmodule
diff --git a/tests/arch/gatemate/mul.ys b/tests/arch/gatemate/mul.ys
new file mode 100644
index 000000000..ded5fe729
--- /dev/null
+++ b/tests/arch/gatemate/mul.ys
@@ -0,0 +1,33 @@
+read_verilog mul.v
+design -save read
+
+hierarchy -top mul_plain
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_plain # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MULT
+select -assert-none t:CC_MULT %% t:* %D
+
+design -load read
+hierarchy -top mul_signed_async
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_signed_async # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MULT
+select -assert-count 1 t:CC_BUFG
+select -assert-count 28 t:CC_DFF
+select -assert-none t:CC_MULT t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top mul_unsigned_sync
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_unsigned_sync # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MULT
+select -assert-count 1 t:CC_BUFG
+select -assert-max 18 t:CC_LUT4
+select -assert-count 18 t:CC_DFF
+select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/mux.ys b/tests/arch/gatemate/mux.ys
new file mode 100644
index 000000000..320ff33d7
--- /dev/null
+++ b/tests/arch/gatemate/mux.ys
@@ -0,0 +1,24 @@
+read_verilog ../common/mux.v
+design -save read
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-max 1 t:CC_LUT2
+select -assert-max 2 t:CC_LUT4
+select -assert-max 1 t:CC_MX2
+select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-max 1 t:CC_LUT3
+select -assert-max 5 t:CC_LUT4
+select -assert-max 1 t:CC_MX2
+select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D
diff --git a/tests/arch/gatemate/run-test.sh b/tests/arch/gatemate/run-test.sh
new file mode 100755
index 000000000..4be4b70ae
--- /dev/null
+++ b/tests/arch/gatemate/run-test.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/tests/arch/gatemate/shifter.ys b/tests/arch/gatemate/shifter.ys
new file mode 100644
index 000000000..0006a298a
--- /dev/null
+++ b/tests/arch/gatemate/shifter.ys
@@ -0,0 +1,10 @@
+read_verilog -D NO_INIT ../common/shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 8 t:CC_DFF
+select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/tribuf.ys b/tests/arch/gatemate/tribuf.ys
new file mode 100644
index 000000000..d900fa5e4
--- /dev/null
+++ b/tests/arch/gatemate/tribuf.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+select -assert-count 2 t:CC_IBUF
+select -assert-max 1 t:CC_LUT1
+select -assert-count 1 t:CC_TOBUF
+select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D
diff --git a/tests/arch/gowin/lutram.ys b/tests/arch/gowin/lutram.ys
index 56f69e7c5..d668783a2 100644
--- a/tests/arch/gowin/lutram.ys
+++ b/tests/arch/gowin/lutram.ys
@@ -7,12 +7,11 @@ memory
 opt -full
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#ERROR: Called with -verify and proof did fail!
-#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
 sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
 
 design -load postopt
 cd lutram_1w1r
-select -assert-count 8 t:RAM16S4
+select -assert-count 8 t:RAM16SDP4
 # other logic present that is not simple
 #select -assert-none t:RAM16S4 %% t:* %D
diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys
index 5855b9d97..eef7e379f 100644
--- a/tests/arch/gowin/tribuf.ys
+++ b/tests/arch/gowin/tribuf.ys
@@ -9,5 +9,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
 select -assert-count 1 t:TBUF
+select -assert-count 1 t:LUT1
 select -assert-count 2 t:IBUF
-select -assert-none t:TBUF t:IBUF %% t:* %D
+select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/ice40/bug2061.ys b/tests/arch/ice40/bug2061.ys
new file mode 100644
index 000000000..7dd7ee6a3
--- /dev/null
+++ b/tests/arch/ice40/bug2061.ys
@@ -0,0 +1,24 @@
+read_verilog <<EOT
+module top #(
+    parameter integer WIDTH = 12
+)(
+    output reg  [WIDTH:0] cnt,
+    input  wire clk,
+    input  wire rst
+);
+    wire last_n;
+
+    assign last_n = cnt[WIDTH];
+
+    always @(posedge clk or posedge rst)
+        if (rst)
+            cnt <= 0;
+        else
+            cnt <= last_n ? ( cnt + { (WIDTH+1){last_n} } ) : 13'h1aaa;
+
+endmodule
+EOT
+
+synth_ice40
+splitnets
+select -assert-count 12 t:SB_CARRY %co:+[CO] t:SB_LUT4 %ci:+[I3] %i
diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
index c32f12315..4920a45e3 100644
--- a/tests/arch/ice40/memories.ys
+++ b/tests/arch/ice40/memories.ys
@@ -1,167 +1,194 @@
 # ================================ RAM ================================
 # RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:SB_RAM40_4K # too inefficient
 select -assert-min 1 t:SB_DFFE
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "Block_RAM" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K # any case works
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "registers" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
 select -assert-min 1 t:SB_DFFE
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set logic_block 1 m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
 select -assert-min 1 t:SB_DFFE
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BROM but this is a RAM
+select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockram.v
+design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+hierarchy -top sync_ram_sdp
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
-select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
 
 # ================================ ROM ================================
 # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
 ## With parameters
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # too inefficient
 select -assert-min 1 t:SB_LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "logic" m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
 select -assert-min 1 t:SB_LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set logic_block 1 m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
 select -assert-min 1 t:SB_LUT4
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
 
-design -reset; read_verilog ../common/blockrom.v
+design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+hierarchy -top sync_rom
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_rom -nobram; cd sync_rom
-select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
diff --git a/tests/arch/intel_alm/add_sub.ys b/tests/arch/intel_alm/add_sub.ys
index 0f552a27c..8f87adf27 100644
--- a/tests/arch/intel_alm/add_sub.ys
+++ b/tests/arch/intel_alm/add_sub.ys
@@ -1,18 +1,18 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 8 t:MISTRAL_ALUT_ARITH
+select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
 
 design -reset
 read_verilog ../common/add_sub.v
 hierarchy -top top
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 8 t:MISTRAL_ALUT_ARITH
+select -assert-count 9 t:MISTRAL_ALUT_ARITH
 select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D
diff --git a/tests/arch/intel_alm/adffs.ys b/tests/arch/intel_alm/adffs.ys
index 4565dcc64..d7487c40b 100644
--- a/tests/arch/intel_alm/adffs.ys
+++ b/tests/arch/intel_alm/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm  -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -15,7 +15,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top adff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -27,7 +27,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -38,7 +38,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top adffn
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -49,7 +49,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -61,7 +61,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 design -load read
 hierarchy -top dffs
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -73,7 +73,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -85,7 +85,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D
 design -load read
 hierarchy -top ndffnr
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/blockram.ys b/tests/arch/intel_alm/blockram.ys
index 610ae1ffd..c157c3165 100644
--- a/tests/arch/intel_alm/blockram.ys
+++ b/tests/arch/intel_alm/blockram.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
-synth_intel_alm -family cyclonev
+synth_intel_alm -family cyclonev -noiopad -noclkbuf
 cd sync_ram_sdp
 select -assert-count 1 t:MISTRAL_M10K
 select -assert-none t:MISTRAL_M10K %% t:* %D
diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys
index 50103fefc..56c9cabb3 100644
--- a/tests/arch/intel_alm/counter.ys
+++ b/tests/arch/intel_alm/counter.ys
@@ -2,11 +2,11 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 2 t:MISTRAL_NOT
+select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
@@ -17,11 +17,11 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 2 t:MISTRAL_NOT
+select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 8 t:MISTRAL_ALUT_ARITH
 select -assert-count 8 t:MISTRAL_FF
 select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D
diff --git a/tests/arch/intel_alm/dffs.ys b/tests/arch/intel_alm/dffs.ys
index 9ae6c637a..34b99f04c 100644
--- a/tests/arch/intel_alm/dffs.ys
+++ b/tests/arch/intel_alm/dffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 hierarchy -top dff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -13,7 +13,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dff
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
@@ -35,7 +35,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D
 design -load read
 hierarchy -top dffe
 proc
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/fsm.ys b/tests/arch/intel_alm/fsm.ys
index e54b5c21e..0aeea450a 100644
--- a/tests/arch/intel_alm/fsm.ys
+++ b/tests/arch/intel_alm/fsm.ys
@@ -3,7 +3,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
@@ -26,7 +26,7 @@ hierarchy -top fsm
 proc
 flatten
 
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
 sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
diff --git a/tests/arch/intel_alm/logic.ys b/tests/arch/intel_alm/logic.ys
index e8b26a524..d34d1bc65 100644
--- a/tests/arch/intel_alm/logic.ys
+++ b/tests/arch/intel_alm/logic.ys
@@ -1,7 +1,7 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -15,7 +15,7 @@ design -reset
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys
index 66f8a1536..9ddb1ec87 100644
--- a/tests/arch/intel_alm/lutram.ys
+++ b/tests/arch/intel_alm/lutram.ys
@@ -2,7 +2,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf
 memory
 opt -full
 
@@ -12,11 +12,10 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
 design -load postopt
 cd lutram_1w1r
 select -assert-count 16 t:MISTRAL_MLAB
-select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
-select -assert-count 17 t:MISTRAL_FF
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+select -assert-count 8 t:MISTRAL_FF
+select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
 
 
 design -reset
@@ -24,7 +23,7 @@ read_verilog ../common/lutram.v
 hierarchy -top lutram_1w1r
 proc
 memory -nomap
-equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf
 memory
 opt -full
 
@@ -34,8 +33,7 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
 design -load postopt
 cd lutram_1w1r
 select -assert-count 16 t:MISTRAL_MLAB
-select -assert-count 1 t:MISTRAL_NOT
 select -assert-count 2 t:MISTRAL_ALUT2
 select -assert-count 8 t:MISTRAL_ALUT3
-select -assert-count 17 t:MISTRAL_FF
-select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+select -assert-count 8 t:MISTRAL_FF
+select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys
index 49934740f..e147d93ac 100644
--- a/tests/arch/intel_alm/mul.ys
+++ b/tests/arch/intel_alm/mul.ys
@@ -2,7 +2,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -16,7 +16,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -28,7 +28,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -40,7 +40,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
@@ -52,7 +52,7 @@ read_verilog ../common/mul.v
 chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52
 hierarchy -top top
 proc
-equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys
index ac3b9b08f..6fb6ae80a 100644
--- a/tests/arch/intel_alm/mux.ys
+++ b/tests/arch/intel_alm/mux.ys
@@ -4,7 +4,7 @@ design -save read
 
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -14,7 +14,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 design -load read
 hierarchy -top mux2
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT6
@@ -34,7 +34,7 @@ select -assert-none t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux4
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT6
@@ -44,7 +44,7 @@ select -assert-none t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -55,7 +55,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux8
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -66,7 +66,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
@@ -78,7 +78,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
 design -load read
 hierarchy -top mux16
 proc
-equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
 select -assert-count 1 t:MISTRAL_ALUT3
diff --git a/tests/arch/intel_alm/quartus_ice.ys b/tests/arch/intel_alm/quartus_ice.ys
index a88226e13..4e1896b82 100644
--- a/tests/arch/intel_alm/quartus_ice.ys
+++ b/tests/arch/intel_alm/quartus_ice.ys
@@ -22,5 +22,5 @@ module top();
 endmodule
 EOT
 
-synth_intel_alm -family cyclone10gx -quartus
+synth_intel_alm -family cyclone10gx -quartus -noiopad -noclkbuf
 select -assert-none w:*[* w:*]*
diff --git a/tests/arch/intel_alm/shifter.ys b/tests/arch/intel_alm/shifter.ys
index e307b5486..77ff98896 100644
--- a/tests/arch/intel_alm/shifter.ys
+++ b/tests/arch/intel_alm/shifter.ys
@@ -2,7 +2,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
@@ -14,7 +14,7 @@ read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:MISTRAL_FF
diff --git a/tests/arch/intel_alm/tribuf.ys b/tests/arch/intel_alm/tribuf.ys
index 7f3b38493..fb5fecb78 100644
--- a/tests/arch/intel_alm/tribuf.ys
+++ b/tests/arch/intel_alm/tribuf.ys
@@ -4,7 +4,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev # equivalency check
+equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
@@ -19,7 +19,7 @@ proc
 tribuf
 flatten
 synth
-equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx # equivalency check
+equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 #Internal cell type used. Need support it.
diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys
index 6c8aa857c..7b7e62d4c 100644
--- a/tests/arch/machxo2/mux.ys
+++ b/tests/arch/machxo2/mux.ys
@@ -35,6 +35,6 @@ proc
 equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 11 t:LUT4
+select -assert-max 12 t:LUT4
 
 select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys
index 9c00a8bcf..fce342e18 100644
--- a/tests/arch/machxo2/tribuf.ys
+++ b/tests/arch/machxo2/tribuf.ys
@@ -6,5 +6,5 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
 select -assert-count 3 t:FACADE_IO
-select -assert-count 1 t:$not
-select -assert-none t:FACADE_IO t:$not %% t:* %D
+select -assert-count 1 t:LUT4
+select -assert-none t:FACADE_IO t:LUT4 %% t:* %D
diff --git a/tests/arch/nexus/lutram.ys b/tests/arch/nexus/lutram.ys
index cd645f717..6e33431b6 100644
--- a/tests/arch/nexus/lutram.ys
+++ b/tests/arch/nexus/lutram.ys
@@ -13,7 +13,7 @@ design -load postopt
 cd lutram_1w1r
 stat
 select -assert-count 8 t:WIDEFN9
-select -assert-count 16 t:LUT4
+select -assert-count 12 t:LUT4
 select -assert-count 8 t:DPR16X4
-select -assert-count 36 t:FD1P3IX
+select -assert-count 8 t:FD1P3IX
 select -assert-none t:DPR16X4 t:FD1P3IX t:WIDEFN9 t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D
diff --git a/tests/arch/quicklogic/.gitignore b/tests/arch/quicklogic/.gitignore
new file mode 100644
index 000000000..9a71dca69
--- /dev/null
+++ b/tests/arch/quicklogic/.gitignore
@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
++*_synth.v
++*_testbench
diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys
new file mode 100644
index 000000000..73ee5cb44
--- /dev/null
+++ b/tests/arch/quicklogic/add_sub.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 2 t:LUT2
+select -assert-count 8 t:LUT3
+select -assert-count 2 t:LUT4
+select -assert-count 8 t:inpad
+select -assert-count 8 t:outpad
+select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/adffs.ys
new file mode 100644
index 000000000..41a175844
--- /dev/null
+++ b/tests/arch/quicklogic/adffs.ys
@@ -0,0 +1,67 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 1 t:inpad
+select -assert-count 1 t:outpad
+select -assert-count 2 t:ckpad
+
+select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT1
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 2 t:inpad
+select -assert-count 1 t:outpad
+select -assert-count 1 t:ckpad
+
+select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 3 t:inpad
+select -assert-count 1 t:outpad
+select -assert-count 1 t:ckpad
+
+select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT1
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 4 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT1 t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/counter.ys
new file mode 100644
index 000000000..2e266417c
--- /dev/null
+++ b/tests/arch/quicklogic/counter.ys
@@ -0,0 +1,18 @@
+read_verilog ../common/counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT1
+select -assert-count 3 t:LUT2
+select -assert-count 5 t:LUT3
+select -assert-count 1 t:LUT4
+select -assert-count 8 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 8 t:outpad
+select -assert-count 2 t:ckpad
+
+select -assert-none t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:outpad t:ckpad %% t:* %D
diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/dffs.ys
new file mode 100644
index 000000000..2e0a34540
--- /dev/null
+++ b/tests/arch/quicklogic/dffs.ys
@@ -0,0 +1,20 @@
+read_verilog ../common/dffs.v
+rename dff my_dff # Work around conflicting module names between test and vendor cells
+rename dffe my_dffe
+design -save read
+
+hierarchy -top my_dff
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-none t:*
+
+design -load read
+hierarchy -top my_dffe
+proc
+equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+
+select -assert-none t:*
\ No newline at end of file
diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/fsm.ys
new file mode 100644
index 000000000..130dacf42
--- /dev/null
+++ b/tests/arch/quicklogic/fsm.ys
@@ -0,0 +1,23 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:LUT2
+select -assert-count 9 t:LUT3
+select -assert-count 4 t:dffepc
+select -assert-count 1 t:logic_0
+select -assert-count 1 t:logic_1
+select -assert-count 3 t:inpad
+select -assert-count 2 t:outpad
+select -assert-count 1 t:ckpad
+
+select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D
diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/latches.ys
new file mode 100644
index 000000000..bcef42990
--- /dev/null
+++ b/tests/arch/quicklogic/latches.ys
@@ -0,0 +1,40 @@
+read_verilog ../common/latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_quicklogic
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 3 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_quicklogic
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 3 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_quicklogic
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:LUT4
+select -assert-count 5 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys
new file mode 100644
index 000000000..4b327c00a
--- /dev/null
+++ b/tests/arch/quicklogic/logic.ys
@@ -0,0 +1,14 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:LUT1
+select -assert-count 6 t:LUT2
+select -assert-count 2 t:LUT3
+select -assert-count 8 t:inpad
+select -assert-count 10 t:outpad
+
+select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys
new file mode 100644
index 000000000..ea17fa99b
--- /dev/null
+++ b/tests/arch/quicklogic/mux.ys
@@ -0,0 +1,52 @@
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 3 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 3 t:LUT3
+select -assert-count 6 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT1
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:mux4x0
+select -assert-count 11 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:mux8x0
+select -assert-count 20 t:inpad
+select -assert-count 1 t:outpad
+
+select -assert-none t:LUT3 t:mux8x0 t:inpad t:outpad %% t:* %D
diff --git a/tests/arch/quicklogic/run-test.sh b/tests/arch/quicklogic/run-test.sh
new file mode 100755
index 000000000..4be4b70ae
--- /dev/null
+++ b/tests/arch/quicklogic/run-test.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/tribuf.ys
new file mode 100644
index 000000000..de763009e
--- /dev/null
+++ b/tests/arch/quicklogic/tribuf.ys
@@ -0,0 +1,13 @@
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+select -assert-count 2 t:inpad
+select -assert-count 1 t:outpad
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:inpad t:outpad t:$_TBUF_ %% t:* %D
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh
index 170078a7f..5d923db56 100755
--- a/tests/arch/run-test.sh
+++ b/tests/arch/run-test.sh
@@ -11,7 +11,7 @@ for arch in ../../techlibs/*; do
 		if [ "${defines[$arch_name]}" ]; then
 			for def in ${defines[$arch_name]}; do
 				echo -n "Test $path -D$def ->"
-				iverilog -t null -I$arch -D$def $path
+				iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path
 				echo " ok"
 			done
 		else
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index 210e87477..0ba3901f7 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -50,10 +50,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
 FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
 endmodule
 EOT
-logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
 logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
-logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
 design -load postopt
 select -assert-count 8 t:FD*
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index ace646af4..3b1919627 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -31,6 +31,7 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 6 t:FDRE
 select -assert-count 1 t:LUT1
-select -assert-count 8 t:LUT4
+select -assert-max 1 t:LUT3
+select -assert-max 8 t:LUT4
 select -assert-count 5 t:MUXF5
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT4 t:MUXF5 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh
index bd44395cb..eca33e490 100644
--- a/tests/arch/xilinx/tribuf.sh
+++ b/tests/arch/xilinx/tribuf.sh
@@ -1,5 +1,5 @@
-! ../../../yosys -qp "synth_xilinx" ../common/tribuf.v
-../../../yosys -qp "synth_xilinx -iopad; \
+../../../yosys -f verilog -qp "synth_xilinx" ../common/tribuf.v
+../../../yosys -f verilog -qp "synth_xilinx -iopad; \
 select -assert-count 2 t:IBUF; \
 select -assert-count 1 t:INV; \
 select -assert-count 1 t:OBUFT" ../common/tribuf.v