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| author | Claire Xen <claire@clairexen.net> | 2022-02-11 16:03:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-11 16:03:12 +0100 |
| commit | 49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch) | |
| tree | d0f20b8def36e551c6735d4fc6033aaa2633fe80 /tests | |
| parent | 90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff) | |
| parent | e0165188669fcef2c5784c9916683889a2164e5d (diff) | |
| download | yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.gz yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.bz2 yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.zip | |
Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'tests')
286 files changed, 7650 insertions, 475 deletions
diff --git a/tests/arch/anlogic/blockram.ys b/tests/arch/anlogic/blockram.ys new file mode 100644 index 000000000..da23409ba --- /dev/null +++ b/tests/arch/anlogic/blockram.ys @@ -0,0 +1,13 @@ +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sp +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +design -load postopt +cd sync_ram_sp + +select -assert-count 1 t:EG_PHY_BRAM +select -assert-none t:EG_PHY_BRAM %% t:* %D diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys index 9ebb75443..fe6135c73 100644 --- a/tests/arch/anlogic/lutram.ys +++ b/tests/arch/anlogic/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -nobram memory opt -full @@ -13,9 +13,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter design -load postopt cd lutram_1w1r -select -assert-count 8 t:AL_MAP_LUT2 -select -assert-count 8 t:AL_MAP_LUT4 -select -assert-count 8 t:AL_MAP_LUT5 -select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 4 t:AL_MAP_LUT3 +select -assert-count 8 t:AL_MAP_LUT6 +select -assert-count 8 t:AL_MAP_SEQ select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT6 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v index 576bd81a6..966e7c2b8 100644 --- a/tests/arch/common/adffs.v +++ b/tests/arch/common/adffs.v @@ -1,7 +1,9 @@ module adff( input d, clk, clr, output reg q ); +`ifndef NO_INIT initial begin q = 0; end +`endif always @( posedge clk, posedge clr ) if ( clr ) q <= 1'b0; @@ -10,9 +12,11 @@ module adff( input d, clk, clr, output reg q ); endmodule module adffn( input d, clk, clr, output reg q ); +`ifndef NO_INIT initial begin q = 0; end +`endif always @( posedge clk, negedge clr ) if ( !clr ) q <= 1'b0; @@ -21,9 +25,11 @@ module adffn( input d, clk, clr, output reg q ); endmodule module dffs( input d, clk, pre, clr, output reg q ); +`ifndef NO_INIT initial begin q = 0; end +`endif always @( posedge clk ) if ( pre ) q <= 1'b1; @@ -32,9 +38,11 @@ module dffs( input d, clk, pre, clr, output reg q ); endmodule module ndffnr( input d, clk, pre, clr, output reg q ); +`ifndef NO_INIT initial begin q = 0; end +`endif always @( negedge clk ) if ( !clr ) q <= 1'b0; diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 9746fd701..1e0a13dc9 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -1,11 +1,11 @@ -module top ( out, clk, reset );
- output [7:0] out;
- input clk, reset;
- reg [7:0] out;
-
- always @(posedge clk, posedge reset)
- if (reset)
- out <= 8'b0;
- else
- out <= out + 1;
-endmodule
+module top ( out, clk, reset ); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) + out <= 8'b0; + else + out <= out + 1; +endmodule diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v index 636252d16..0c607af50 100644 --- a/tests/arch/common/dffs.v +++ b/tests/arch/common/dffs.v @@ -4,9 +4,11 @@ module dff ( input d, clk, output reg q ); endmodule module dffe( input d, clk, en, output reg q ); +`ifndef NO_INIT initial begin q = 0; end +`endif always @( posedge clk ) if ( en ) q <= d; diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v index 9d3fbb64a..cf1c21a58 100644 --- a/tests/arch/common/fsm.v +++ b/tests/arch/common/fsm.v @@ -1,51 +1,51 @@ - module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
- input clock,reset,req_0,req_1;
- output gnt_0,gnt_1;
- wire clock,reset,req_0,req_1;
- reg gnt_0,gnt_1;
-
- parameter SIZE = 3;
- parameter IDLE = 3'b001;
- parameter GNT0 = 3'b010;
- parameter GNT1 = 3'b100;
- parameter GNT2 = 3'b101;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
- state <= #1 IDLE;
- gnt_0 <= 0;
- gnt_1 <= 0;
- end
- else
- case(state)
- IDLE : if (req_0 == 1'b1) begin
- state <= #1 GNT0;
- gnt_0 <= 1;
- end else if (req_1 == 1'b1) begin
- gnt_1 <= 1;
- state <= #1 GNT0;
- end else begin
- state <= #1 IDLE;
- end
- GNT0 : if (req_0 == 1'b1) begin
- state <= #1 GNT0;
- end else begin
- gnt_0 <= 0;
- state <= #1 IDLE;
- end
- GNT1 : if (req_1 == 1'b1) begin
- state <= #1 GNT2;
- gnt_1 <= req_0;
- end
- GNT2 : if (req_0 == 1'b1) begin
- state <= #1 GNT1;
- gnt_1 <= req_1;
- end
- default : state <= #1 IDLE;
- endcase
- end
-endmodule
+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3; + parameter IDLE = 3'b001; + parameter GNT0 = 3'b010; + parameter GNT1 = 3'b100; + parameter GNT2 = 3'b101; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end + else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end +endmodule diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index cace3b588..06e63c9af 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -1,11 +1,17 @@ -module top(out, clk, in);
- output [7:0] out;
- input signed clk, in;
- reg signed [7:0] out = 0;
-
- always @(posedge clk)
- begin
- out <= out >> 1;
- out[7] <= in;
- end
-endmodule
+module top(out, clk, in); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out; + +`ifndef NO_INIT + initial begin + out = 0; + end +`endif + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end +endmodule diff --git a/tests/arch/ecp5/bug2731.ys b/tests/arch/ecp5/bug2731.ys new file mode 100644 index 000000000..c609cea3b --- /dev/null +++ b/tests/arch/ecp5/bug2731.ys @@ -0,0 +1,7 @@ +read_verilog -icells <<EOF +module top(input c, r, input [1:0] d, output reg [1:0] q); +TRELLIS_FF #(.REGSET("SET")) ff1(.CLK(c), .LSR(r), .DI(d[0]), .Q(q[0])); +TRELLIS_FF #(.REGSET("SET")) ff2(.CLK(c), .LSR(r), .DI(d[1]), .Q(q[1])); +endmodule +EOF +synth_ecp5 -abc9 -dff diff --git a/tests/arch/ecp5/lutram.ys b/tests/arch/ecp5/lutram.ys index e1ae7abd5..9bef37c68 100644 --- a/tests/arch/ecp5/lutram.ys +++ b/tests/arch/ecp5/lutram.ys @@ -11,9 +11,9 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r -select -assert-count 24 t:L6MUX21 -select -assert-count 71 t:LUT4 -select -assert-count 32 t:PFUMX +select -assert-count 8 t:L6MUX21 +select -assert-count 36 t:LUT4 +select -assert-count 16 t:PFUMX select -assert-count 8 t:TRELLIS_DPR16X4 -select -assert-count 35 t:TRELLIS_FF +select -assert-count 8 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys index f55bf01d2..44651ba25 100644 --- a/tests/arch/ecp5/memories.ys +++ b/tests/arch/ecp5/memories.ys @@ -1,328 +1,379 @@ # ================================ RAM ================================ # RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:PDPW16KD ## With parameters -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:PDPW16KD # too inefficient select -assert-count 9 t:TRELLIS_DPR16X4 -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "block_ram" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:PDPW16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "Block_RAM" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:PDPW16KD # any case works -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set ram_block 1 m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:PDPW16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "registers" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly select -assert-count 180 t:TRELLIS_FF -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set logic_block 1 m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly select -assert-count 180 t:TRELLIS_FF -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_romstyle "ebr" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BROM but this is a RAM +select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set rom_block 1 m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BROM but this is a RAM +select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "block_ram" m:memory synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set ram_block 1 m:memory synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled # RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:DP16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 9 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:DP16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 4 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:DP16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 13 -set DATA_WIDTH 2 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:DP16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:DP16KD ## With parameters -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:DP16KD # too inefficient select -assert-count 5 t:TRELLIS_DPR16X4 -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "block_ram" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:DP16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "Block_RAM" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:DP16KD # any case works -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set ram_block 1 m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:DP16KD -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "registers" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:DP16KD # requested FFRAM explicitly select -assert-count 90 t:TRELLIS_FF -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set logic_block 1 m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:DP16KD # requested FFRAM explicitly select -assert-count 90 t:TRELLIS_FF -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_romstyle "ebr" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BROM but this is a RAM +select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set rom_block 1 m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BROM but this is a RAM +select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "block_ram" m:memory synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set ram_block 1 m:memory synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled # RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4 -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:TRELLIS_DPR16X4 ## With parameters -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "distributed" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:TRELLIS_DPR16X4 -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "registers" m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly select -assert-count 68 t:TRELLIS_FF -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set logic_block 1 m:memory synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly select -assert-count 68 t:TRELLIS_FF -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "distributed" m:memory synth_ecp5 -top sync_ram_sdp -nolutram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested LUTRAM but LUTRAM is disabled +select -assert-count 1 t:$mem_v2 # requested LUTRAM but LUTRAM is disabled # ================================ ROM ================================ # ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 1 t:PDPW16KD ## With parameters -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:PDPW16KD # too inefficient select -assert-min 18 t:LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom setattr -set syn_romstyle "ebr" m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 1 t:PDPW16KD -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom setattr -set rom_block 1 m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 1 t:PDPW16KD -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom setattr -set syn_romstyle "logic" m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly select -assert-min 18 t:LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom setattr -set logic_block 1 m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly select -assert-min 18 t:LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom setattr -set syn_ramstyle "block_ram" m:memory synth_ecp5 -top sync_rom; cd sync_rom -select -assert-count 1 t:$mem # requested BRAM but this is a ROM +select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom setattr -set ram_block 1 m:memory synth_ecp5 -top sync_rom; cd sync_rom -select -assert-count 1 t:$mem # requested BRAM but this is a ROM +select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom setattr -set syn_ramstyle "block_rom" m:memory synth_ecp5 -top sync_rom -nobram; cd sync_rom -select -assert-count 1 t:$mem # requested BROM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom +hierarchy -top sync_rom setattr -set rom_block 1 m:memory synth_ecp5 -top sync_rom -nobram; cd sync_rom -select -assert-count 1 t:$mem # requested BROM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled # ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 1 t:DP16KD ## With parameters -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:DP16KD # too inefficient select -assert-min 9 t:LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom setattr -set syn_romstyle "ebr" m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 1 t:DP16KD -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom setattr -set rom_block 1 m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 1 t:DP16KD -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom setattr -set syn_romstyle "logic" m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:DP16KD # requested LUTROM explicitly select -assert-min 9 t:LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom setattr -set logic_block 1 m:memory synth_ecp5 -top sync_rom; cd sync_rom select -assert-count 0 t:DP16KD # requested LUTROM explicitly select -assert-min 9 t:LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom setattr -set syn_ramstyle "block_ram" m:memory synth_ecp5 -top sync_rom; cd sync_rom -select -assert-count 1 t:$mem # requested BRAM but this is a ROM +select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom setattr -set ram_block 1 m:memory synth_ecp5 -top sync_rom; cd sync_rom -select -assert-count 1 t:$mem # requested BRAM but this is a ROM +select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom setattr -set syn_ramstyle "block_rom" m:memory synth_ecp5 -top sync_rom -nobram; cd sync_rom -select -assert-count 1 t:$mem # requested BROM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom +hierarchy -top sync_rom setattr -set rom_block 1 m:memory synth_ecp5 -top sync_rom -nobram; cd sync_rom -select -assert-count 1 t:$mem # requested BROM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index 92463aa32..db63dda5f 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -15,9 +15,9 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 1 t:L6MUX21 -select -assert-count 4 t:LUT4 -select -assert-count 2 t:PFUMX +select -assert-max 1 t:L6MUX21 +select -assert-max 4 t:LUT4 +select -assert-max 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D @@ -27,9 +27,9 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 1 t:L6MUX21 -select -assert-count 7 t:LUT4 -select -assert-count 2 t:PFUMX +select -assert-max 1 t:L6MUX21 +select -assert-max 7 t:LUT4 +select -assert-max 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D @@ -39,8 +39,8 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 8 t:L6MUX21 -select -assert-count 26 t:LUT4 -select -assert-count 12 t:PFUMX +select -assert-max 12 t:L6MUX21 +select -assert-max 34 t:LUT4 +select -assert-max 17 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/arch/gatemate/.gitignore b/tests/arch/gatemate/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/arch/gatemate/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys new file mode 100644 index 000000000..bf261ba5a --- /dev/null +++ b/tests/arch/gatemate/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:CC_ADDF +select -assert-max 4 t:CC_LUT1 +select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys new file mode 100644 index 000000000..b2ded6e9d --- /dev/null +++ b/tests/arch/gatemate/adffs.ys @@ -0,0 +1,43 @@ +read_verilog -D NO_INIT ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-max 1 t:CC_LUT2 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-max 1 t:CC_LUT2 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D diff --git a/tests/arch/gatemate/counter.ys b/tests/arch/gatemate/counter.ys new file mode 100644 index 000000000..77ed858b3 --- /dev/null +++ b/tests/arch/gatemate/counter.ys @@ -0,0 +1,12 @@ +read_verilog ../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:CC_ADDF +select -assert-count 1 t:CC_BUFG +select -assert-count 8 t:CC_DFF +select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D diff --git a/tests/arch/gatemate/dffs.ys b/tests/arch/gatemate/dffs.ys new file mode 100644 index 000000000..022322419 --- /dev/null +++ b/tests/arch/gatemate/dffs.ys @@ -0,0 +1,21 @@ +read_verilog -D NO_INIT ../common/dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_DFF +select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys new file mode 100644 index 000000000..6b43ead7a --- /dev/null +++ b/tests/arch/gatemate/fsm.ys @@ -0,0 +1,20 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad +async2sync +miter -equiv -make_assert -flatten gold gate miter +stat +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 1 t:CC_BUFG +select -assert-count 6 t:CC_DFF +select -assert-max 5 t:CC_LUT2 +select -assert-max 4 t:CC_LUT3 +select -assert-max 9 t:CC_LUT4 +select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D diff --git a/tests/arch/gatemate/latches.ys b/tests/arch/gatemate/latches.ys new file mode 100644 index 000000000..5f64c6db5 --- /dev/null +++ b/tests/arch/gatemate/latches.ys @@ -0,0 +1,29 @@ +read_verilog ../common/latches.v +design -save read + +hierarchy -top latchp +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_DLT +select -assert-none t:CC_DLT %% t:* %D + +design -load read +hierarchy -top latchn +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_DLT +select -assert-none t:CC_DLT %% t:* %D + +design -load read +hierarchy -top latchsr +proc +equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_DLT +select -assert-max 2 t:CC_LUT3 +select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys new file mode 100644 index 000000000..026406bc8 --- /dev/null +++ b/tests/arch/gatemate/logic.ys @@ -0,0 +1,10 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-max 1 t:CC_LUT1 +select -assert-max 6 t:CC_LUT2 +select -assert-max 2 t:CC_LUT4 +select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D diff --git a/tests/arch/gatemate/memory.ys b/tests/arch/gatemate/memory.ys new file mode 100644 index 000000000..e919920f8 --- /dev/null +++ b/tests/arch/gatemate/memory.ys @@ -0,0 +1,34 @@ +# 512 x 40 bit -> CC_BRAM_20K SDP RAM +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_ram_sdp +synth_gatemate -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_BRAM_20K + +# 512 x 80 bit -> CC_BRAM_40K SDP RAM +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_ram_sdp +synth_gatemate -top sync_ram_sdp -noiopad +cd sync_ram_sdp +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_BRAM_40K + +# 512 x 40 bit -> CC_BRAM_20K SDP ROM +design -reset +read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 40 sync_rom +synth_gatemate -top sync_rom -noiopad +cd sync_rom +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_BRAM_20K + +# 512 x 80 bit -> CC_BRAM_40K SDP ROM +design -reset +read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 80 sync_rom +synth_gatemate -top sync_rom -noiopad +cd sync_rom +select -assert-count 1 t:CC_BUFG +select -assert-count 1 t:CC_BRAM_40K diff --git a/tests/arch/gatemate/mul.v b/tests/arch/gatemate/mul.v new file mode 100644 index 000000000..55e8f9006 --- /dev/null +++ b/tests/arch/gatemate/mul.v @@ -0,0 +1,79 @@ + +module mul_plain(a, b, p); + + parameter M = 6; + parameter N = 6; + + input wire [M-1:0] a; + input wire [N-1:0] b; + output wire [M+N-1:0] p; + + assign p = a * b; + +endmodule + +module mul_signed_async (clk, rst, en, a, b, p); + + parameter M = 8; + parameter N = 6; + + input wire signed clk, rst, en; + input wire signed [M-1:0] a; + input wire signed [N-1:0] b; + output reg signed [M+N-1:0] p; + + reg signed [M-1:0] a_reg; + reg signed [N-1:0] b_reg; + + // signed M*N multiplier with + // - input and output pipeline registers + // - asynchronous reset (active high) + // - clock enable (active high) + always @(posedge clk or posedge rst) + begin + if (rst) begin + a_reg <= 0; + b_reg <= 0; + p <= 0; + end + else if (en) begin + a_reg <= a; + b_reg <= b; + p <= a_reg * b_reg; + end + end + +endmodule + +module mul_unsigned_sync (clk, rst, en, a, b, p); + + parameter M = 6; + parameter N = 3; + + input wire clk, rst, en; + input wire [M-1:0] a; + input wire [N-1:0] b; + output reg [M+N-1:0] p; + + reg [M-1:0] a_reg; + reg [N-1:0] b_reg; + + // unsigned M*N multiplier with + // - input and output pipeline registers + // - synchronous reset (active high) + // - clock enable (active high) + always @(posedge clk) + begin + if (rst) begin + a_reg <= 0; + b_reg <= 0; + p <= 0; + end + else if (en) begin + a_reg <= a; + b_reg <= b; + p <= a_reg * b_reg; + end + end + +endmodule diff --git a/tests/arch/gatemate/mul.ys b/tests/arch/gatemate/mul.ys new file mode 100644 index 000000000..ded5fe729 --- /dev/null +++ b/tests/arch/gatemate/mul.ys @@ -0,0 +1,33 @@ +read_verilog mul.v +design -save read + +hierarchy -top mul_plain +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_plain # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_MULT +select -assert-none t:CC_MULT %% t:* %D + +design -load read +hierarchy -top mul_signed_async +proc +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_signed_async # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_MULT +select -assert-count 1 t:CC_BUFG +select -assert-count 28 t:CC_DFF +select -assert-none t:CC_MULT t:CC_BUFG t:CC_DFF %% t:* %D + +design -load read +hierarchy -top mul_unsigned_sync +proc +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned_sync # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_MULT +select -assert-count 1 t:CC_BUFG +select -assert-max 18 t:CC_LUT4 +select -assert-count 18 t:CC_DFF +select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D diff --git a/tests/arch/gatemate/mux.ys b/tests/arch/gatemate/mux.ys new file mode 100644 index 000000000..320ff33d7 --- /dev/null +++ b/tests/arch/gatemate/mux.ys @@ -0,0 +1,24 @@ +read_verilog ../common/mux.v +design -save read + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-max 1 t:CC_LUT2 +select -assert-max 2 t:CC_LUT4 +select -assert-max 1 t:CC_MX2 +select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-max 1 t:CC_LUT3 +select -assert-max 5 t:CC_LUT4 +select -assert-max 1 t:CC_MX2 +select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D diff --git a/tests/arch/gatemate/run-test.sh b/tests/arch/gatemate/run-test.sh new file mode 100755 index 000000000..4be4b70ae --- /dev/null +++ b/tests/arch/gatemate/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../../gen-tests-makefile.sh +run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" diff --git a/tests/arch/gatemate/shifter.ys b/tests/arch/gatemate/shifter.ys new file mode 100644 index 000000000..0006a298a --- /dev/null +++ b/tests/arch/gatemate/shifter.ys @@ -0,0 +1,10 @@ +read_verilog -D NO_INIT ../common/shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:CC_BUFG +select -assert-count 8 t:CC_DFF +select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D diff --git a/tests/arch/gatemate/tribuf.ys b/tests/arch/gatemate/tribuf.ys new file mode 100644 index 000000000..d900fa5e4 --- /dev/null +++ b/tests/arch/gatemate/tribuf.ys @@ -0,0 +1,13 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/gatemate/cells_sim.v -map +/simcells.v synth_gatemate # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 2 t:CC_IBUF +select -assert-max 1 t:CC_LUT1 +select -assert-count 1 t:CC_TOBUF +select -assert-none t:CC_IBUF t:CC_LUT1 t:CC_TOBUF %% t:* %D diff --git a/tests/arch/gowin/lutram.ys b/tests/arch/gowin/lutram.ys index 56f69e7c5..d668783a2 100644 --- a/tests/arch/gowin/lutram.ys +++ b/tests/arch/gowin/lutram.ys @@ -7,12 +7,11 @@ memory opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd lutram_1w1r -select -assert-count 8 t:RAM16S4 +select -assert-count 8 t:RAM16SDP4 # other logic present that is not simple #select -assert-none t:RAM16S4 %% t:* %D diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys index 5855b9d97..eef7e379f 100644 --- a/tests/arch/gowin/tribuf.ys +++ b/tests/arch/gowin/tribuf.ys @@ -9,5 +9,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd tristate # Constrain all select calls below inside the top module #Internal cell type used. Need support it. select -assert-count 1 t:TBUF +select -assert-count 1 t:LUT1 select -assert-count 2 t:IBUF -select -assert-none t:TBUF t:IBUF %% t:* %D +select -assert-none t:TBUF t:IBUF t:LUT1 %% t:* %D
\ No newline at end of file diff --git a/tests/arch/ice40/bug2061.ys b/tests/arch/ice40/bug2061.ys new file mode 100644 index 000000000..7dd7ee6a3 --- /dev/null +++ b/tests/arch/ice40/bug2061.ys @@ -0,0 +1,24 @@ +read_verilog <<EOT +module top #( + parameter integer WIDTH = 12 +)( + output reg [WIDTH:0] cnt, + input wire clk, + input wire rst +); + wire last_n; + + assign last_n = cnt[WIDTH]; + + always @(posedge clk or posedge rst) + if (rst) + cnt <= 0; + else + cnt <= last_n ? ( cnt + { (WIDTH+1){last_n} } ) : 13'h1aaa; + +endmodule +EOT + +synth_ice40 +splitnets +select -assert-count 12 t:SB_CARRY %co:+[CO] t:SB_LUT4 %ci:+[I3] %i diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index c32f12315..4920a45e3 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -1,167 +1,194 @@ # ================================ RAM ================================ # RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K ## With parameters -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:SB_RAM40_4K # too inefficient select -assert-min 1 t:SB_DFFE -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "Block_RAM" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K # any case works -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set ram_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "registers" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly select -assert-min 1 t:SB_DFFE -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set logic_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly select -assert-min 1 t:SB_DFFE -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_romstyle "ebr" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BROM but this is a RAM +select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set rom_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BROM but this is a RAM +select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled -design -reset; read_verilog ../common/blockram.v +design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +hierarchy -top sync_ram_sdp setattr -set ram_block 1 m:memory synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp -select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled # ================================ ROM ================================ # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom +hierarchy -top sync_rom synth_ice40 -top sync_rom; cd sync_rom select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom +hierarchy -top sync_rom synth_ice40 -top sync_rom; cd sync_rom select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom synth_ice40 -top sync_rom; cd sync_rom select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom +hierarchy -top sync_rom synth_ice40 -top sync_rom; cd sync_rom select -assert-count 1 t:SB_RAM40_4K ## With parameters -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom synth_ice40 -top sync_rom; cd sync_rom select -assert-count 0 t:SB_RAM40_4K # too inefficient select -assert-min 1 t:SB_LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom setattr -set syn_romstyle "ebr" m:memory synth_ice40 -top sync_rom; cd sync_rom select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom setattr -set rom_block 1 m:memory synth_ice40 -top sync_rom; cd sync_rom select -assert-count 1 t:SB_RAM40_4K -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom setattr -set syn_romstyle "logic" m:memory synth_ice40 -top sync_rom; cd sync_rom select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly select -assert-min 1 t:SB_LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom setattr -set logic_block 1 m:memory synth_ice40 -top sync_rom; cd sync_rom select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly select -assert-min 1 t:SB_LUT4 -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_rom; cd sync_rom -select -assert-count 1 t:$mem # requested BRAM but this is a ROM +select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom setattr -set ram_block 1 m:memory synth_ice40 -top sync_rom; cd sync_rom -select -assert-count 1 t:$mem # requested BRAM but this is a ROM +select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom setattr -set syn_romstyle "ebr" m:memory synth_ice40 -top sync_rom -nobram; cd sync_rom -select -assert-count 1 t:$mem # requested BROM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled -design -reset; read_verilog ../common/blockrom.v +design -reset; read_verilog -defer ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +hierarchy -top sync_rom setattr -set rom_block 1 m:memory synth_ice40 -top sync_rom -nobram; cd sync_rom -select -assert-count 1 t:$mem # requested BROM but BRAM is disabled +select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled diff --git a/tests/arch/intel_alm/add_sub.ys b/tests/arch/intel_alm/add_sub.ys index 0f552a27c..8f87adf27 100644 --- a/tests/arch/intel_alm/add_sub.ys +++ b/tests/arch/intel_alm/add_sub.ys @@ -1,18 +1,18 @@ read_verilog ../common/add_sub.v hierarchy -top top -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module stat -select -assert-count 8 t:MISTRAL_ALUT_ARITH +select -assert-count 9 t:MISTRAL_ALUT_ARITH select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D design -reset read_verilog ../common/add_sub.v hierarchy -top top -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module stat -select -assert-count 8 t:MISTRAL_ALUT_ARITH +select -assert-count 9 t:MISTRAL_ALUT_ARITH select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D diff --git a/tests/arch/intel_alm/adffs.ys b/tests/arch/intel_alm/adffs.ys index 4565dcc64..d7487c40b 100644 --- a/tests/arch/intel_alm/adffs.ys +++ b/tests/arch/intel_alm/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -15,7 +15,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D design -load read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -27,7 +27,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -38,7 +38,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -49,7 +49,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -61,7 +61,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -73,7 +73,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -85,7 +85,7 @@ select -assert-none t:MISTRAL_FF t:MISTRAL_NOT %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF diff --git a/tests/arch/intel_alm/blockram.ys b/tests/arch/intel_alm/blockram.ys index 610ae1ffd..c157c3165 100644 --- a/tests/arch/intel_alm/blockram.ys +++ b/tests/arch/intel_alm/blockram.ys @@ -1,6 +1,6 @@ read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp -synth_intel_alm -family cyclonev +synth_intel_alm -family cyclonev -noiopad -noclkbuf cd sync_ram_sdp select -assert-count 1 t:MISTRAL_M10K select -assert-none t:MISTRAL_M10K %% t:* %D diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys index 50103fefc..56c9cabb3 100644 --- a/tests/arch/intel_alm/counter.ys +++ b/tests/arch/intel_alm/counter.ys @@ -2,11 +2,11 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 2 t:MISTRAL_NOT +select -assert-count 1 t:MISTRAL_NOT select -assert-count 8 t:MISTRAL_ALUT_ARITH select -assert-count 8 t:MISTRAL_FF select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D @@ -17,11 +17,11 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 2 t:MISTRAL_NOT +select -assert-count 1 t:MISTRAL_NOT select -assert-count 8 t:MISTRAL_ALUT_ARITH select -assert-count 8 t:MISTRAL_FF select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D diff --git a/tests/arch/intel_alm/dffs.ys b/tests/arch/intel_alm/dffs.ys index 9ae6c637a..34b99f04c 100644 --- a/tests/arch/intel_alm/dffs.ys +++ b/tests/arch/intel_alm/dffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top dff proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -13,7 +13,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D design -load read hierarchy -top dff proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF @@ -35,7 +35,7 @@ select -assert-none t:MISTRAL_FF %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_FF diff --git a/tests/arch/intel_alm/fsm.ys b/tests/arch/intel_alm/fsm.ys index e54b5c21e..0aeea450a 100644 --- a/tests/arch/intel_alm/fsm.ys +++ b/tests/arch/intel_alm/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev +equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf async2sync miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter @@ -26,7 +26,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx +equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf async2sync miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/tests/arch/intel_alm/logic.ys b/tests/arch/intel_alm/logic.ys index e8b26a524..d34d1bc65 100644 --- a/tests/arch/intel_alm/logic.ys +++ b/tests/arch/intel_alm/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -15,7 +15,7 @@ design -reset read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys index 66f8a1536..9ddb1ec87 100644 --- a/tests/arch/intel_alm/lutram.ys +++ b/tests/arch/intel_alm/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram +equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf memory opt -full @@ -12,11 +12,10 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r select -assert-count 16 t:MISTRAL_MLAB -select -assert-count 1 t:MISTRAL_NOT select -assert-count 2 t:MISTRAL_ALUT2 select -assert-count 8 t:MISTRAL_ALUT3 -select -assert-count 17 t:MISTRAL_FF -select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D +select -assert-count 8 t:MISTRAL_FF +select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D design -reset @@ -24,7 +23,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram +equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram -noiopad -noclkbuf memory opt -full @@ -34,8 +33,7 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r select -assert-count 16 t:MISTRAL_MLAB -select -assert-count 1 t:MISTRAL_NOT select -assert-count 2 t:MISTRAL_ALUT2 select -assert-count 8 t:MISTRAL_ALUT3 -select -assert-count 17 t:MISTRAL_FF -select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D +select -assert-count 8 t:MISTRAL_FF +select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys index 49934740f..e147d93ac 100644 --- a/tests/arch/intel_alm/mul.ys +++ b/tests/arch/intel_alm/mul.ys @@ -2,7 +2,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -16,7 +16,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -28,7 +28,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 17 -set Y_WIDTH 17 -set A_WIDTH 34 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -40,7 +40,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module @@ -52,7 +52,7 @@ read_verilog ../common/mul.v chparam -set X_WIDTH 26 -set Y_WIDTH 26 -set A_WIDTH 52 hierarchy -top top proc -equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys index ac3b9b08f..6fb6ae80a 100644 --- a/tests/arch/intel_alm/mux.ys +++ b/tests/arch/intel_alm/mux.ys @@ -4,7 +4,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 @@ -14,7 +14,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D design -load read hierarchy -top mux2 proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 @@ -24,7 +24,7 @@ select -assert-none t:MISTRAL_ALUT3 %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT6 @@ -34,7 +34,7 @@ select -assert-none t:MISTRAL_ALUT6 %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT6 @@ -44,7 +44,7 @@ select -assert-none t:MISTRAL_ALUT6 %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 @@ -55,7 +55,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 @@ -66,7 +66,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT6 %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 @@ -78,7 +78,7 @@ select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_ALUT3 diff --git a/tests/arch/intel_alm/quartus_ice.ys b/tests/arch/intel_alm/quartus_ice.ys index a88226e13..4e1896b82 100644 --- a/tests/arch/intel_alm/quartus_ice.ys +++ b/tests/arch/intel_alm/quartus_ice.ys @@ -22,5 +22,5 @@ module top(); endmodule EOT -synth_intel_alm -family cyclone10gx -quartus +synth_intel_alm -family cyclone10gx -quartus -noiopad -noclkbuf select -assert-none w:*[* w:*]* diff --git a/tests/arch/intel_alm/shifter.ys b/tests/arch/intel_alm/shifter.ys index e307b5486..77ff98896 100644 --- a/tests/arch/intel_alm/shifter.ys +++ b/tests/arch/intel_alm/shifter.ys @@ -2,7 +2,7 @@ read_verilog ../common/shifter.v hierarchy -top top proc flatten -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 8 t:MISTRAL_FF @@ -14,7 +14,7 @@ read_verilog ../common/shifter.v hierarchy -top top proc flatten -equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 8 t:MISTRAL_FF diff --git a/tests/arch/intel_alm/tribuf.ys b/tests/arch/intel_alm/tribuf.ys index 7f3b38493..fb5fecb78 100644 --- a/tests/arch/intel_alm/tribuf.ys +++ b/tests/arch/intel_alm/tribuf.ys @@ -4,7 +4,7 @@ proc tribuf flatten synth -equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev # equivalency check +equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module #Internal cell type used. Need support it. @@ -19,7 +19,7 @@ proc tribuf flatten synth -equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx # equivalency check +equiv_opt -assert -map +/simcells.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module #Internal cell type used. Need support it. diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 6c8aa857c..7b7e62d4c 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -35,6 +35,6 @@ proc equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 11 t:LUT4 +select -assert-max 12 t:LUT4 select -assert-none t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys index 9c00a8bcf..fce342e18 100644 --- a/tests/arch/machxo2/tribuf.ys +++ b/tests/arch/machxo2/tribuf.ys @@ -6,5 +6,5 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module select -assert-count 3 t:FACADE_IO -select -assert-count 1 t:$not -select -assert-none t:FACADE_IO t:$not %% t:* %D +select -assert-count 1 t:LUT4 +select -assert-none t:FACADE_IO t:LUT4 %% t:* %D diff --git a/tests/arch/nexus/lutram.ys b/tests/arch/nexus/lutram.ys index cd645f717..6e33431b6 100644 --- a/tests/arch/nexus/lutram.ys +++ b/tests/arch/nexus/lutram.ys @@ -13,7 +13,7 @@ design -load postopt cd lutram_1w1r stat select -assert-count 8 t:WIDEFN9 -select -assert-count 16 t:LUT4 +select -assert-count 12 t:LUT4 select -assert-count 8 t:DPR16X4 -select -assert-count 36 t:FD1P3IX +select -assert-count 8 t:FD1P3IX select -assert-none t:DPR16X4 t:FD1P3IX t:WIDEFN9 t:LUT4 t:INV t:IB t:OB t:VLO t:VHI %% t:* %D diff --git a/tests/arch/quicklogic/.gitignore b/tests/arch/quicklogic/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/arch/quicklogic/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys new file mode 100644 index 000000000..73ee5cb44 --- /dev/null +++ b/tests/arch/quicklogic/add_sub.ys @@ -0,0 +1,11 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:LUT2 +select -assert-count 8 t:LUT3 +select -assert-count 2 t:LUT4 +select -assert-count 8 t:inpad +select -assert-count 8 t:outpad +select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/adffs.ys new file mode 100644 index 000000000..41a175844 --- /dev/null +++ b/tests/arch/quicklogic/adffs.ys @@ -0,0 +1,67 @@ +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:dffepc +select -assert-count 1 t:logic_0 +select -assert-count 1 t:logic_1 +select -assert-count 1 t:inpad +select -assert-count 1 t:outpad +select -assert-count 2 t:ckpad + +select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT1 +select -assert-count 1 t:dffepc +select -assert-count 1 t:logic_0 +select -assert-count 1 t:logic_1 +select -assert-count 2 t:inpad +select -assert-count 1 t:outpad +select -assert-count 1 t:ckpad + +select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT2 +select -assert-count 1 t:dffepc +select -assert-count 1 t:logic_0 +select -assert-count 1 t:logic_1 +select -assert-count 3 t:inpad +select -assert-count 1 t:outpad +select -assert-count 1 t:ckpad + +select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT1 +select -assert-count 1 t:LUT2 +select -assert-count 1 t:dffepc +select -assert-count 1 t:logic_0 +select -assert-count 1 t:logic_1 +select -assert-count 4 t:inpad +select -assert-count 1 t:outpad + +select -assert-none t:LUT1 t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad %% t:* %D diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/counter.ys new file mode 100644 index 000000000..2e266417c --- /dev/null +++ b/tests/arch/quicklogic/counter.ys @@ -0,0 +1,18 @@ +read_verilog ../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT1 +select -assert-count 3 t:LUT2 +select -assert-count 5 t:LUT3 +select -assert-count 1 t:LUT4 +select -assert-count 8 t:dffepc +select -assert-count 1 t:logic_0 +select -assert-count 1 t:logic_1 +select -assert-count 8 t:outpad +select -assert-count 2 t:ckpad + +select -assert-none t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:dffepc t:logic_0 t:logic_1 t:outpad t:ckpad %% t:* %D diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/dffs.ys new file mode 100644 index 000000000..2e0a34540 --- /dev/null +++ b/tests/arch/quicklogic/dffs.ys @@ -0,0 +1,20 @@ +read_verilog ../common/dffs.v +rename dff my_dff # Work around conflicting module names between test and vendor cells +rename dffe my_dffe +design -save read + +hierarchy -top my_dff +proc +equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-none t:* + +design -load read +hierarchy -top my_dffe +proc +equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module + +select -assert-none t:*
\ No newline at end of file diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/fsm.ys new file mode 100644 index 000000000..130dacf42 --- /dev/null +++ b/tests/arch/quicklogic/fsm.ys @@ -0,0 +1,23 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic +async2sync +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT2 +select -assert-count 9 t:LUT3 +select -assert-count 4 t:dffepc +select -assert-count 1 t:logic_0 +select -assert-count 1 t:logic_1 +select -assert-count 3 t:inpad +select -assert-count 2 t:outpad +select -assert-count 1 t:ckpad + +select -assert-none t:LUT2 t:LUT3 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* %D diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/latches.ys new file mode 100644 index 000000000..bcef42990 --- /dev/null +++ b/tests/arch/quicklogic/latches.ys @@ -0,0 +1,40 @@ +read_verilog ../common/latches.v +design -save read + +hierarchy -top latchp +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_quicklogic +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 3 t:inpad +select -assert-count 1 t:outpad + +select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_quicklogic +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 3 t:inpad +select -assert-count 1 t:outpad + +select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_quicklogic +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT2 +select -assert-count 1 t:LUT4 +select -assert-count 5 t:inpad +select -assert-count 1 t:outpad + +select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys new file mode 100644 index 000000000..4b327c00a --- /dev/null +++ b/tests/arch/quicklogic/logic.ys @@ -0,0 +1,14 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT1 +select -assert-count 6 t:LUT2 +select -assert-count 2 t:LUT3 +select -assert-count 8 t:inpad +select -assert-count 10 t:outpad + +select -assert-none t:LUT1 t:LUT2 t:LUT3 t:inpad t:outpad %% t:* %D diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys new file mode 100644 index 000000000..ea17fa99b --- /dev/null +++ b/tests/arch/quicklogic/mux.ys @@ -0,0 +1,52 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 3 t:inpad +select -assert-count 1 t:outpad + +select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 3 t:LUT3 +select -assert-count 6 t:inpad +select -assert-count 1 t:outpad + +select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT1 +select -assert-count 1 t:LUT3 +select -assert-count 2 t:mux4x0 +select -assert-count 11 t:inpad +select -assert-count 1 t:outpad + +select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 2 t:mux8x0 +select -assert-count 20 t:inpad +select -assert-count 1 t:outpad + +select -assert-none t:LUT3 t:mux8x0 t:inpad t:outpad %% t:* %D diff --git a/tests/arch/quicklogic/run-test.sh b/tests/arch/quicklogic/run-test.sh new file mode 100755 index 000000000..4be4b70ae --- /dev/null +++ b/tests/arch/quicklogic/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../../gen-tests-makefile.sh +run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/tribuf.ys new file mode 100644 index 000000000..de763009e --- /dev/null +++ b/tests/arch/quicklogic/tribuf.ys @@ -0,0 +1,13 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 2 t:inpad +select -assert-count 1 t:outpad +select -assert-count 1 t:$_TBUF_ +select -assert-none t:inpad t:outpad t:$_TBUF_ %% t:* %D diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh index 170078a7f..5d923db56 100755 --- a/tests/arch/run-test.sh +++ b/tests/arch/run-test.sh @@ -11,7 +11,7 @@ for arch in ../../techlibs/*; do if [ "${defines[$arch_name]}" ]; then for def in ${defines[$arch_name]}; do echo -n "Test $path -D$def ->" - iverilog -t null -I$arch -D$def $path + iverilog -t null -I$arch -D$def -DNO_ICE40_DEFAULT_ASSIGNMENTS $path echo " ok" done else diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index 210e87477..0ba3901f7 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -50,10 +50,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6])); FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7])); endmodule EOT -logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 -logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 +logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 +logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 -logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 +logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=.*1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt select -assert-count 8 t:FD* diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index ace646af4..3b1919627 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -31,6 +31,7 @@ stat select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE select -assert-count 1 t:LUT1 -select -assert-count 8 t:LUT4 +select -assert-max 1 t:LUT3 +select -assert-max 8 t:LUT4 select -assert-count 5 t:MUXF5 -select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT4 t:MUXF5 %% t:* %D +select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh index bd44395cb..eca33e490 100644 --- a/tests/arch/xilinx/tribuf.sh +++ b/tests/arch/xilinx/tribuf.sh @@ -1,5 +1,5 @@ -! ../../../yosys -qp "synth_xilinx" ../common/tribuf.v -../../../yosys -qp "synth_xilinx -iopad; \ +../../../yosys -f verilog -qp "synth_xilinx" ../common/tribuf.v +../../../yosys -f verilog -qp "synth_xilinx -iopad; \ select -assert-count 2 t:IBUF; \ select -assert-count 1 t:INV; \ select -assert-count 1 t:OBUFT" ../common/tribuf.v diff --git a/tests/bind/.gitignore b/tests/bind/.gitignore new file mode 100644 index 000000000..8355de9dc --- /dev/null +++ b/tests/bind/.gitignore @@ -0,0 +1,2 @@ +*.log +run-test.mk diff --git a/tests/bind/basic.sv b/tests/bind/basic.sv new file mode 100644 index 000000000..ce0d04c48 --- /dev/null +++ b/tests/bind/basic.sv @@ -0,0 +1,20 @@ +// A basic example of the bind construct + +module foo (input logic a, input logic b, output logic c); + // Magic happens here... +endmodule + +module bar (input a, input b, output c); + assign c = a ^ b; +endmodule + +module top (); + logic u, v, w; + foo foo_i (.a (u), .b (v), .c (w)); + + bind foo bar bound_i (.*); + + always_comb begin + assert(w == u ^ v); + end +endmodule diff --git a/tests/bind/basic.ys b/tests/bind/basic.ys new file mode 100644 index 000000000..266fa4e48 --- /dev/null +++ b/tests/bind/basic.ys @@ -0,0 +1 @@ +read_verilog -sv basic.sv diff --git a/tests/bind/cell_list.sv b/tests/bind/cell_list.sv new file mode 100644 index 000000000..c0da13d29 --- /dev/null +++ b/tests/bind/cell_list.sv @@ -0,0 +1,26 @@ +// An example of specifying multiple bind instances in a single directive. This +// also uses explicit bound names. + +module foo (input logic a0, input logic b0, output logic c0, + input logic a1, input logic b1, output logic c1); + // Magic happens here... +endmodule + +module bar (input a, input b, output c); + assign c = a ^ b; +endmodule + +module top (); + logic u0, v0, w0; + logic u1, v1, w1; + + foo foo0 (.a0 (u0), .b0 (v0), .c0 (w0), + .a1 (u1), .b1 (v1), .c1 (w1)); + + bind foo bar bar0 (.a(a0), .b(b0), .c(c0)), bar1 (.a(a1), .b(b1), .c(c1)); + + always_comb begin + assert(w0 == u0 ^ v0); + assert(w1 == u1 ^ v1); + end +endmodule diff --git a/tests/bind/cell_list.ys b/tests/bind/cell_list.ys new file mode 100644 index 000000000..9afd9a941 --- /dev/null +++ b/tests/bind/cell_list.ys @@ -0,0 +1 @@ +read_verilog -sv cell_list.sv diff --git a/tests/bind/hier.sv b/tests/bind/hier.sv new file mode 100644 index 000000000..fd3bc62b8 --- /dev/null +++ b/tests/bind/hier.sv @@ -0,0 +1,20 @@ +// An example of the bind construct using a hierarchical reference starting with $root + +module foo (input logic a, input logic b, output logic c); + // Magic happens here... +endmodule + +module bar (input a, input b, output c); + assign c = a ^ b; +endmodule + +module top (); + logic u, v, w; + foo foo_i (.a (u), .b (v), .c (w)); + + always_comb begin + assert(w == u ^ v); + end +endmodule + +bind $root.top.foo_i bar bound_i (.*); diff --git a/tests/bind/hier.ys b/tests/bind/hier.ys new file mode 100644 index 000000000..c19fba100 --- /dev/null +++ b/tests/bind/hier.ys @@ -0,0 +1 @@ +read_verilog -sv hier.sv diff --git a/tests/bind/inst_list.sv b/tests/bind/inst_list.sv new file mode 100644 index 000000000..e0077caec --- /dev/null +++ b/tests/bind/inst_list.sv @@ -0,0 +1,24 @@ +// An example of specifying multiple bind targets with an instance list + +module foo (input logic a, input logic b, output logic c); + // Magic happens here... +endmodule + +module bar (input a, input b, output c); + assign c = a ^ b; +endmodule + +module top (); + logic u0, v0, w0; + logic u1, v1, w1; + + foo foo0 (.a (u0), .b (v0), .c (w0)); + foo foo1 (.a (u1), .b (v1), .c (w1)); + + bind foo : foo0, foo1 bar bound_i (.*); + + always_comb begin + assert(w0 == u0 ^ v0); + assert(w1 == u1 ^ v1); + end +endmodule diff --git a/tests/bind/inst_list.ys b/tests/bind/inst_list.ys new file mode 100644 index 000000000..ac1385b83 --- /dev/null +++ b/tests/bind/inst_list.ys @@ -0,0 +1 @@ +read_verilog -sv inst_list.sv diff --git a/tests/bind/param.sv b/tests/bind/param.sv new file mode 100644 index 000000000..c7793527a --- /dev/null +++ b/tests/bind/param.sv @@ -0,0 +1,26 @@ +// An example showing how parameters get inferred when binding + +module foo (input logic a, input logic b, output logic c); + parameter doit = 1; + + // Magic happens here... +endmodule + +module bar (input a, input b, output c); + parameter doit = 1; + + assign c = doit ? a ^ b : 0; +endmodule + +module top (input u0, input v0, output w0, + input u1, input v1, output w1); + foo #(.doit (0)) foo0 (.a (u0), .b (v0), .c (w0)); + foo #(.doit (1)) foo1 (.a (u1), .b (v1), .c (w1)); + + bind foo bar #(.doit (doit)) bound_i (.*); + + always_comb begin + assert (w0 == '0); + assert (w1 == u1 ^ v1); + end +endmodule diff --git a/tests/bind/param.ys b/tests/bind/param.ys new file mode 100644 index 000000000..a43d05759 --- /dev/null +++ b/tests/bind/param.ys @@ -0,0 +1 @@ +read_verilog -sv param.sv diff --git a/tests/bind/run-test.sh b/tests/bind/run-test.sh new file mode 100755 index 000000000..ea56b70f0 --- /dev/null +++ b/tests/bind/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/bind/toplevel.sv b/tests/bind/toplevel.sv new file mode 100644 index 000000000..328edcf67 --- /dev/null +++ b/tests/bind/toplevel.sv @@ -0,0 +1,20 @@ +// The bind construct occurring at top-level in the script + +module foo (input logic a, input logic b, output logic c); + // Magic happens here... +endmodule + +module bar (input a, input b, output c); + assign c = a ^ b; +endmodule + +module top (); + logic u, v, w; + foo foo_i (.a (u), .b (v), .c (w)); + + always_comb begin + assert(w == u ^ v); + end +endmodule + +bind top.foo_i bar bound_i (.*); diff --git a/tests/bind/toplevel.ys b/tests/bind/toplevel.ys new file mode 100644 index 000000000..11c0ada19 --- /dev/null +++ b/tests/bind/toplevel.ys @@ -0,0 +1 @@ +read_verilog -sv toplevel.sv diff --git a/tests/blif/.gitignore b/tests/blif/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/blif/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/blif/bug2729.ys b/tests/blif/bug2729.ys new file mode 100644 index 000000000..0cbc21aa0 --- /dev/null +++ b/tests/blif/bug2729.ys @@ -0,0 +1,20 @@ +read_verilog <<EOF + +module cell (input [2:12] I, output [5:-5] O); +endmodule + +module top(input [10:0] A, output [10:0] B); +cell my_cell(.I(A), .O(B)); +endmodule + +EOF + +write_blif tmp-bug2729.blif +delete top +read_blif -wideports tmp-bug2729.blif +!rm tmp-bug2729.blif +rename -enumerate t:cell +dump +cd top +connect -assert -port _0_ I A +connect -assert -port _0_ O B diff --git a/tests/blif/run-test.sh b/tests/blif/run-test.sh new file mode 100755 index 000000000..44ce7e674 --- /dev/null +++ b/tests/blif/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.ys; do + echo "Running $x.." + ../../yosys -ql ${x%.ys}.log $x +done diff --git a/tests/bram/generate.py b/tests/bram/generate.py index def0b23c1..79dd500a3 100644 --- a/tests/bram/generate.py +++ b/tests/bram/generate.py @@ -93,18 +93,22 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next): tb_dout = list() tb_addrlist = list() + addrmask = (1 << abits) - 1 + for i in range(10): - tb_addrlist.append(random.randrange(1048576)) + tb_addrlist.append(random.randrange(1048576) & addrmask) t = random.randrange(1048576) for i in range(10): - tb_addrlist.append(t ^ (1 << i)) + tb_addrlist.append((t ^ (1 << i)) & addrmask) v_stmts.append("(* nomem2reg *) reg [%d:0] memory [0:%d];" % (dbits-1, 2**abits-1)) portindex = 0 last_always_hdr = (-1, "") + addr2en = {} + for p1 in range(groups): for p2 in range(ports[p1]): pf = "%c%d" % (chr(ord("A") + p1), p2 + 1) @@ -143,6 +147,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next): v_stmts.append("input [%d:0] %sEN;" % (enable[p1]-1, pf)) tb_decls.append("reg [%d:0] %sEN;" % (enable[p1]-1, pf)) tb_din.append("%sEN" % pf) + addr2en["%sADDR" % pf] = "%sEN" % pf assign_op = "<=" if clocks[p1] == 0: @@ -247,10 +252,23 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next): print(" #100;", file=tb_f) print(" $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" % (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f) - for p in tb_din: - print(" %s <= %d;" % (p, random.randrange(1048576)), file=tb_f) + a2e = {} for p in tb_addr: - print(" %s <= %d;" % (p, random.choice(tb_addrlist)), file=tb_f) + addr = random.choice(tb_addrlist) + if p in addr2en: + if addr not in a2e: + a2e[addr] = [] + a2e[addr].append(addr2en[p]) + print(" %s <= %d;" % (p, addr), file=tb_f) + enzero = set() + for v in a2e.values(): + x = random.choice(v) + for s in v: + if s != x: + enzero.add(s) + for p in tb_din: + val = 0 if p in enzero else random.randrange(1048576) + print(" %s <= %d;" % (p, val), file=tb_f) print(" #900;", file=tb_f) print(" end", file=tb_f) diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 98a45b613..429a79e3c 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,6 +1,6 @@ #!/bin/bash set -e -../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ +../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v diff --git a/tests/memories/read_arst.v b/tests/memories/read_arst.v new file mode 100644 index 000000000..6100cc4a7 --- /dev/null +++ b/tests/memories/read_arst.v @@ -0,0 +1,27 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk +// expect-rd-en \re +// expect-rd-arst-sig \reset +// expect-rd-arst-val 8'01011010 +// expect-rd-init-val 8'00111100 + +module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata); + +reg [7:0] bram[0:255]; +initial rdata = 8'h3c; + +always @(posedge clk) begin + if (we) + bram[addr] <= wdata; +end + +always @(posedge clk, posedge reset) begin + if (reset) + rdata <= 8'h5a; + else if (re) + rdata <= bram[addr]; +end + +endmodule + diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v index 4f2e7e1cd..8b609c552 100644 --- a/tests/memories/read_two_mux.v +++ b/tests/memories/read_two_mux.v @@ -1,6 +1,9 @@ // expect-wr-ports 1 // expect-rd-ports 1 -// expect-no-rd-clk +// expect-rd-clk \clk +// expect-rd-en \re +// expect-rd-srst-sig \reset +// expect-rd-srst-val 8'00000000 module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata); diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh index 376f5bf79..c65066a9c 100755 --- a/tests/memories/run-test.sh +++ b/tests/memories/run-test.sh @@ -18,11 +18,15 @@ ${MAKE:-make} -f ../tools/autotest.mk SEED="$seed" EXTRA_FLAGS="$abcopt" *.v for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do echo -n "Testing expectations for $f .." - ../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem" $f + ../../yosys -f verilog -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem_v2" $f if grep -q expect-wr-ports $f; then grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp || { echo " ERROR: Unexpected number of write ports."; false; } fi + if grep -q expect-wr-wide-continuation $f; then + grep -q "parameter \\\\WR_WIDE_CONTINUATION $(gawk '/expect-wr-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected write wide continuation."; false; } + fi if grep -q expect-rd-ports $f; then grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp || { echo " ERROR: Unexpected number of read ports."; false; } @@ -31,6 +35,34 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp || { echo " ERROR: Unexpected read clock."; false; } fi + if grep -q expect-rd-en $f; then + grep -q "connect \\\\RD_EN \\$(gawk '/expect-rd-en/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected read enable."; false; } + fi + if grep -q expect-rd-srst-sig $f; then + grep -q "connect \\\\RD_SRST \\$(gawk '/expect-rd-srst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected read sync reset."; false; } + fi + if grep -q expect-rd-srst-val $f; then + grep -q "parameter \\\\RD_SRST_VALUE $(gawk '/expect-rd-srst-val/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected read sync reset value."; false; } + fi + if grep -q expect-rd-arst-sig $f; then + grep -q "connect \\\\RD_ARST \\$(gawk '/expect-rd-arst-sig/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected read async reset."; false; } + fi + if grep -q expect-rd-arst-val $f; then + grep -q "parameter \\\\RD_ARST_VALUE $(gawk '/expect-rd-arst-val/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected read async reset value."; false; } + fi + if grep -q expect-rd-init-val $f; then + grep -q "parameter \\\\RD_INIT_VALUE $(gawk '/expect-rd-init-val/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected read init value."; false; } + fi + if grep -q expect-rd-wide-continuation $f; then + grep -q "parameter \\\\RD_WIDE_CONTINUATION $(gawk '/expect-rd-wide-continuation/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected read wide continuation."; false; } + fi if grep -q expect-no-rd-clk $f; then grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp || { echo " ERROR: Expected no read clock."; false; } diff --git a/tests/memories/trans_addr_enable.v b/tests/memories/trans_addr_enable.v new file mode 100644 index 000000000..f366f41ad --- /dev/null +++ b/tests/memories/trans_addr_enable.v @@ -0,0 +1,21 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk + +module top(input clk, we, rae, input [7:0] addr, wd, output [7:0] rd); + +reg [7:0] mem[0:255]; + +reg [7:0] rra; + +always @(posedge clk) begin + if (we) + mem[addr] <= wd; + + if (rae) + rra <= addr; +end + +assign rd = mem[rra]; + +endmodule diff --git a/tests/memories/trans_sdp.v b/tests/memories/trans_sdp.v new file mode 100644 index 000000000..b89f2ccf0 --- /dev/null +++ b/tests/memories/trans_sdp.v @@ -0,0 +1,21 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk +// expect-rd-en \re + +module top(input clk, we, re, input [7:0] ra, wa, wd, output reg [7:0] rd); + +reg [7:0] mem[0:255]; + +always @(posedge clk) begin + if (we) + mem[wa] <= wd; + + if (re) begin + rd <= mem[ra]; + if (we && ra == wa) + rd <= wd; + end +end + +endmodule diff --git a/tests/memories/trans_sp.v b/tests/memories/trans_sp.v new file mode 100644 index 000000000..ddd41a13e --- /dev/null +++ b/tests/memories/trans_sp.v @@ -0,0 +1,21 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk +// expect-rd-en \re + +module top(input clk, we, re, input [7:0] addr, wd, output reg [7:0] rd); + +reg [7:0] mem[0:255]; + +always @(posedge clk) begin + if (we) + mem[addr] <= wd; + + if (re) begin + rd <= mem[addr]; + if (we) + rd <= wd; + end +end + +endmodule diff --git a/tests/memories/wide_all.v b/tests/memories/wide_all.v new file mode 100644 index 000000000..f7bc3e5ce --- /dev/null +++ b/tests/memories/wide_all.v @@ -0,0 +1,36 @@ +// expect-wr-ports 2 +// expect-rd-ports 1 +// expect-wr-wide-continuation 2'10 + +module test( + input clk, + input [3:0] we, + input [6:0] ra, + input [5:0] wa, + input [31:0] wd, + output [15:0] rd +); + +reg [7:0] mem[3:254]; + +assign rd[7:0] = mem[{ra, 1'b0}]; +assign rd[15:0] = mem[{ra, 1'b1}]; + +initial begin + mem[5] = 8'h12; + mem[6] = 8'h34; + mem[7] = 8'h56; +end + +always @(posedge clk) begin + if (we[0]) + mem[{wa, 2'b00}] <= wd[7:0]; + if (we[1]) + mem[{wa, 2'b01}] <= wd[15:8]; + if (we[2]) + mem[{wa, 2'b10}] <= wd[23:16]; + if (we[3]) + mem[{wa, 2'b11}] <= wd[31:24]; +end + +endmodule diff --git a/tests/memories/wide_read_async.v b/tests/memories/wide_read_async.v new file mode 100644 index 000000000..aecdb1938 --- /dev/null +++ b/tests/memories/wide_read_async.v @@ -0,0 +1,27 @@ +// expect-wr-ports 1 +// expect-rd-ports 4 +// expect-rd-wide-continuation 4'1110 + +module test( + input clk, + input we, + input [5:0] ra, + input [7:0] wa, + input [7:0] wd, + output [31:0] rd +); + +reg [7:0] mem[0:255]; + +assign rd[7:0] = mem[{ra, 2'b00}]; +assign rd[15:8] = mem[{ra, 2'b01}]; +assign rd[23:16] = mem[{ra, 2'b10}]; +assign rd[31:24] = mem[{ra, 2'b11}]; + +always @(posedge clk) begin + if (we) + mem[wa] <= wd; +end + +endmodule + diff --git a/tests/memories/wide_read_mixed.v b/tests/memories/wide_read_mixed.v new file mode 100644 index 000000000..c36db3d31 --- /dev/null +++ b/tests/memories/wide_read_mixed.v @@ -0,0 +1,46 @@ +// expect-wr-ports 1 +// expect-rd-ports 4 +// expect-rd-wide-continuation 4'1110 +// expect-rd-srst-val 32'10000111011001010100001100100001 +// expect-rd-init-val 32'10101011110011011110111110101011 + +// In this testcase, the byte-wide read ports are merged into a single +// word-wide port despite mismatched transparency, with soft transparency +// logic inserted on half the port to preserve the semantics. + +module test( + input clk, + input re, rr, + input we, + input [5:0] ra, + input [7:0] wa, + input [7:0] wd, + output reg [31:0] rd +); + +reg [7:0] mem[0:255]; + +initial rd = 32'habcdefab; + +always @(posedge clk) begin + if (rr) begin + rd <= 32'h87654321; + end else if (re) begin + rd[7:0] <= mem[{ra, 2'b00}]; + rd[15:8] <= mem[{ra, 2'b01}]; + rd[23:16] <= mem[{ra, 2'b10}]; + rd[31:24] <= mem[{ra, 2'b11}]; + if (we && wa == {ra, 2'b00}) + rd [7:0] <= wd; + if (we && wa == {ra, 2'b01}) + rd [15:8] <= wd; + end +end + +always @(posedge clk) begin + if (we) + mem[wa] <= wd; +end + +endmodule + diff --git a/tests/memories/wide_read_sync.v b/tests/memories/wide_read_sync.v new file mode 100644 index 000000000..54ba3f256 --- /dev/null +++ b/tests/memories/wide_read_sync.v @@ -0,0 +1,32 @@ +// expect-wr-ports 1 +// expect-rd-ports 4 +// expect-rd-wide-continuation 4'1110 + +module test( + input clk, + input re, + input we, + input [5:0] ra, + input [7:0] wa, + input [7:0] wd, + output reg [31:0] rd +); + +reg [7:0] mem[0:255]; + +always @(posedge clk) begin + if (re) begin + rd[7:0] <= mem[{ra, 2'b00}]; + rd[15:8] <= mem[{ra, 2'b01}]; + rd[23:16] <= mem[{ra, 2'b10}]; + rd[31:24] <= mem[{ra, 2'b11}]; + end +end + +always @(posedge clk) begin + if (we) + mem[wa] <= wd; +end + +endmodule + diff --git a/tests/memories/wide_read_trans.v b/tests/memories/wide_read_trans.v new file mode 100644 index 000000000..fe3293500 --- /dev/null +++ b/tests/memories/wide_read_trans.v @@ -0,0 +1,40 @@ +// expect-wr-ports 1 +// expect-rd-ports 4 +// expect-rd-wide-continuation 4'1110 + +module test( + input clk, + input re, + input we, + input [5:0] ra, + input [7:0] wa, + input [7:0] wd, + output reg [31:0] rd +); + +reg [7:0] mem[0:255]; + +always @(posedge clk) begin + if (re) begin + rd[7:0] <= mem[{ra, 2'b00}]; + rd[15:8] <= mem[{ra, 2'b01}]; + rd[23:16] <= mem[{ra, 2'b10}]; + rd[31:24] <= mem[{ra, 2'b11}]; + if (we && wa == {ra, 2'b00}) + rd [7:0] <= wd; + if (we && wa == {ra, 2'b01}) + rd [15:8] <= wd; + if (we && wa == {ra, 2'b10}) + rd [23:16] <= wd; + if (we && wa == {ra, 2'b11}) + rd [31:24] <= wd; + end +end + +always @(posedge clk) begin + if (we) + mem[wa] <= wd; +end + +endmodule + diff --git a/tests/memories/wide_thru_priority.v b/tests/memories/wide_thru_priority.v new file mode 100644 index 000000000..10c0d837b --- /dev/null +++ b/tests/memories/wide_thru_priority.v @@ -0,0 +1,29 @@ +// expect-wr-ports 3 +// expect-rd-ports 1 +// expect-wr-wide-continuation 3'010 + +module test( + input clk, + input we1, we2, + input [5:0] ra, + input [4:0] wa1, + input [5:0] wa2, + input [15:0] wd1, + input [7:0] wd2, + output [7:0] rd +); + +reg [7:0] mem[0:63]; + +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) + mem[{wa1, 1'b0}] <= wd1[7:0]; + if (we2) + mem[wa2] <= wd2; + if (we1) + mem[{wa1, 1'b1}] <= wd1[15:8]; +end + +endmodule diff --git a/tests/memories/wide_write.v b/tests/memories/wide_write.v new file mode 100644 index 000000000..5c4cc41f9 --- /dev/null +++ b/tests/memories/wide_write.v @@ -0,0 +1,29 @@ +// expect-wr-ports 4 +// expect-rd-ports 1 +// expect-wr-wide-continuation 4'1110 + +module test( + input clk, + input [3:0] we, + input [7:0] ra, + input [5:0] wa, + input [31:0] wd, + output [7:0] rd +); + +reg [7:0] mem[0:255]; + +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we[0]) + mem[{wa, 2'b00}] <= wd[7:0]; + if (we[1]) + mem[{wa, 2'b01}] <= wd[15:8]; + if (we[2]) + mem[{wa, 2'b10}] <= wd[23:16]; + if (we[3]) + mem[{wa, 2'b11}] <= wd[31:24]; +end + +endmodule diff --git a/tests/opt/bug1854.ys b/tests/opt/bug1854.ys new file mode 100644 index 000000000..00a36ae94 --- /dev/null +++ b/tests/opt/bug1854.ys @@ -0,0 +1,17 @@ +read_verilog << EOT +module top(input clk, input [3:0] addr, output reg [0:0] dout); + reg [1:0] mem[0:15]; + initial begin + mem[0] = 2'b00; + mem[1] = 2'b01; + mem[2] = 2'b10; + mem[3] = 2'b11; + end + always @(posedge clk) + dout <= mem[addr]; +endmodule +EOT + +prep -rdff + +select -assert-none t:$dff diff --git a/tests/opt/bug2623.ys b/tests/opt/bug2623.ys new file mode 100644 index 000000000..2ff23ea6f --- /dev/null +++ b/tests/opt/bug2623.ys @@ -0,0 +1,14 @@ +read_rtlil << EOT + +module \top + wire output 1 \a + wire width 0 $dummy + cell \abc \abc + connect \a \a + connect \b $dummy + end +end + +EOT + +opt_clean diff --git a/tests/opt/bug2765.ys b/tests/opt/bug2765.ys new file mode 100644 index 000000000..7cb790bd7 --- /dev/null +++ b/tests/opt/bug2765.ys @@ -0,0 +1,34 @@ +read_verilog << EOT + +module top(...); + +input clk; +input [3:0] wa; +input [15:0] wd; +input [3:0] ra; +output [15:0] rd; + +reg [15:0] mem[0:15]; + +integer i; +reg x; + +always @(posedge clk) begin + for (i = 0; i < 2; i = i + 1) begin + x = i == 1; + if (x) + mem[wa] <= wd; + end +end + +assign rd = mem[ra]; + +endmodule + +EOT + +proc +opt +select -assert-count 2 t:$memwr_v2 +opt_mem +select -assert-count 1 t:$memwr_v2 diff --git a/tests/opt/bug2766.ys b/tests/opt/bug2766.ys new file mode 100644 index 000000000..c7aa916f4 --- /dev/null +++ b/tests/opt/bug2766.ys @@ -0,0 +1,101 @@ +# Case 1. + +read_verilog << EOT + +module top(...); + +input clk; +input sel; +input [3:0] ra; +input [3:0] wa; +input wd; +output [3:0] rd; + +reg [3:0] mem[0:15]; + +integer i; +initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= i; +end + +assign rd = mem[ra]; + +always @(posedge clk) begin + mem[wa] <= {4{sel ? wd : mem[wa][0]}}; +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_clean + +design -save start +memory_map +design -save preopt + +design -load start +opt_mem_feedback +memory_map +design -save postopt + +equiv_opt -assert -run prepare: : + + + +design -reset + +# Case 2. + +read_verilog << EOT + +module top(...); + +input clk; +input s1; +input s2; +input s3; +input [3:0] ra; +input [3:0] wa; +input wd; +output rd; + +reg mem[0:15]; + +integer i; +initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= ^i; +end + +assign rd = mem[ra]; + +wire ta = s1 ? wd : mem[wa]; +wire tb = s2 ? wd : ta; +wire tc = s3 ? tb : ta; + +always @(posedge clk) begin + mem[wa] <= tc; +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_clean + +design -save start +memory_map +design -save preopt + +design -load start +opt_mem_feedback +memory_map +design -save postopt + +equiv_opt -assert -run prepare: : diff --git a/tests/opt/bug2824.ys b/tests/opt/bug2824.ys new file mode 100644 index 000000000..9d0d1e9e5 --- /dev/null +++ b/tests/opt/bug2824.ys @@ -0,0 +1,7 @@ +read_verilog -icells << EOT +module top(input I, output O); +$pmux #(.WIDTH(1), .S_WIDTH(2)) m (.S({I, 1'b0}), .A(1'b0), .B({I, 1'b0}), .Y(O)); +endmodule +EOT + +equiv_opt -assert opt_muxtree diff --git a/tests/opt/bug2920.ys b/tests/opt/bug2920.ys new file mode 100644 index 000000000..a8281a73a --- /dev/null +++ b/tests/opt/bug2920.ys @@ -0,0 +1,42 @@ +read_ilang <<EOT + +module \mod + wire input 1 \clk + attribute \init 2'00 + wire width 2 $q1 + attribute \init 2'00 + wire width 2 $q2 + wire output 2 width 4 \q + cell $dff $ff1 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk + connect \D 1'0 + connect \Q $q1 [0] + end + cell $dff $ff2 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk + connect \D 1'0 + connect \Q $q2 [0] + end + cell $dff $ff3 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 2 + connect \CLK \clk + connect \D 2'00 + connect \Q { $q1 [1] $q2 [1] } + end + connect \q [0] $q1 [0] + connect \q [1] $q2 [0] + connect \q [2] $q1 [1] + connect \q [3] $q2 [1] +end + +EOT + +opt_clean +opt_merge +opt_dff +opt_clean diff --git a/tests/opt/bug3047.ys b/tests/opt/bug3047.ys new file mode 100644 index 000000000..6713877ce --- /dev/null +++ b/tests/opt/bug3047.ys @@ -0,0 +1,12 @@ +read_verilog << EOT + +module test (A, B, C, D, Y); + input A, B, C, D; + output Y; + assign Y = A^B^C^D^A; +endmodule + +EOT + +techmap +equiv_opt -assert extract_reduce diff --git a/tests/opt/bug3117.ys b/tests/opt/bug3117.ys new file mode 100644 index 000000000..177b3ab9a --- /dev/null +++ b/tests/opt/bug3117.ys @@ -0,0 +1,34 @@ +read_verilog << EOT + +module test (...); + +input [7:1] wa1; +input [7:1] wa2; +input [7:0] ra; +output [7:0] rd; +input clk; +input we1, we2; +input [15:0] wd1, wd2; + +reg [7:0] mem [0:255]; + +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) begin + mem[{wa1, 1'b0}] <= wd1[7:0]; + mem[{wa1, 1'b1}] <= wd1[15:8]; + end else begin + mem[{wa2, 1'b0}] <= wd2[7:0]; + mem[{wa2, 1'b1}] <= wd2[15:8]; + end +end + +endmodule + +EOT + +proc +opt +memory_share +select -assert-count 1 t:$memwr_v2 diff --git a/tests/opt/memory_dff_trans.ys b/tests/opt/memory_dff_trans.ys new file mode 100644 index 000000000..102b36f26 --- /dev/null +++ b/tests/opt/memory_dff_trans.ys @@ -0,0 +1,874 @@ +# Good case 1: single port. + +read_verilog << EOT + +module top( + input [3:0] addr, + input [3:0] wd, + input we, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we) begin + mem[addr] <= wd; + rd <= wd; + end else begin + rd <= mem[addr]; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=1'b1 r:RD_COLLISION_X_MASK=1'b0 %i %i + +design -reset + +# Good case 2: single port, exclusive. + +read_verilog << EOT + +module top( + input [3:0] addr, + input [3:0] wd, + input we, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we) begin + mem[addr] <= wd; + end else begin + rd <= mem[addr]; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=1'b0 r:RD_COLLISION_X_MASK=1'b1 %i %i + +design -reset + +# Good case 3: proper bypass muxes. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we1 && wa1 == ra) + rd <= wd1; + if (we2 && wa2 == ra) + rd <= wd2; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i + +design -reset + +# Good case 4: proper bypass mux, but only one. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we1 && wa1 == ra) + rd <= wd1; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b01 r:RD_COLLISION_X_MASK=2'b00 %i %i + +design -reset + +# Good case 5: proper bypass mux, but the other one. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we2 && wa2 == ra) + rd <= wd2; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b00 %i %i + +design -reset + +# Good case 6: 'x mux. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we1 && wa1 == ra) + rd <= 4'hx; + if (we2 && wa2 == ra) + rd <= wd2; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b01 %i %i + +design -reset + +# Good case 7: uncollidable addresses. + +read_verilog << EOT + +module top( + input [3:0] addr, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +wire [3:0] wa1 = addr; +wire [3:0] wa2 = addr + 1; +wire [3:0] ra = addr + 2; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b00 r:RD_COLLISION_X_MASK=2'b11 %i %i + +design -reset + +# Good case 8: uncollidable addresses, but still have soft transparency logic. + +read_verilog << EOT + +module top( + input [3:0] addr, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +wire [3:0] wa1 = addr; +wire [3:0] wa2 = addr + 1; +wire [3:0] ra = addr + 2; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we1 && wa1 == ra) + rd <= wd1; + if (we2 && wa2 == ra) + rd <= wd2; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b00 r:RD_COLLISION_X_MASK=2'b11 %i %i + +design -reset + +# Bad case 1: broken bypass signal. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we1 && wa1 == ra) + rd <= wd1; + if (we2 && wa2 == ra && we1) + rd <= wd2; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +logger -expect log "FF found, but with a mux select that doesn't seem to correspond to transparency logic" 1 +memory_dff +logger -check-expected +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i + +design -reset + +# Bad case 2: bad data signal. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we1 && wa1 == ra) + rd <= wd1; + if (we2 && wa2 == ra) + rd <= wd1; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +logger -expect log "FF found, but with a mux data input that doesn't seem to correspond to transparency logic" 1 +memory_dff +logger -check-expected +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i + +design -reset + +# Bad case 3: priority mismatch. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we2 && wa2 == ra) + rd <= wd2; + if (we1 && wa1 == ra) + rd <= wd1; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +logger -expect log "FF found, but transparency logic priority doesn't match write priority." 1 +memory_dff +logger -check-expected +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i + +design -reset + +# Good case 10: priority mismatch, but since the second value is 'x, it's still OK. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we2 && wa2 == ra) + rd <= wd2; + if (we1 && wa1 == ra) + rd <= 4'hx; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b10 r:RD_COLLISION_X_MASK=2'b01 %i %i + +design -reset + +# Good case 11: priority mismatch, but since three-way collision cannot happen, it's still OK. + +read_verilog << EOT + +module top( + input [3:0] addr, + input [1:0] mode, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] wa1, wa2, ra; + +always @* begin + case (mode) + 0: begin + wa1 = addr+1; + wa2 = addr; + ra = addr; + end + 1: begin + wa1 = addr; + wa2 = addr+1; + ra = addr; + end + 2: begin + wa1 = addr; + wa2 = addr; + ra = addr+1; + end + 3: begin + wa1 = addr; + wa2 = addr+1; + ra = addr+2; + end + endcase +end + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we2 && wa2 == ra) + rd <= wd2; + if (we1 && wa1 == ra) + rd <= wd1; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i + +design -reset + +# Bad case 4: half of the port is transparent. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; + if (re) begin + rd <= mem[ra]; + if (we1 && wa1 == ra) + rd <= wd1; + if (we2 && wa2 == ra) + rd[3:2] <= wd2[3:2]; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +logger -expect log "FF found, but soft transparency logic is inconsistent for port 1." 1 +memory_dff +logger -check-expected +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_CLK_ENABLE=1'b0 %i + +design -reset + +# Good case 12: like above, but the other bits aren't changed by the port anyway. + +read_verilog << EOT + +module top( + input [3:0] ra, + input [3:0] wa1, + input [3:0] wa2, + input [3:0] wd1, + input [3:0] wd2, + input we1, we2, + input re, + input clk, + output reg [3:0] rd, +); + +reg [3:0] mem[0:15]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2][3:2] <= wd2[3:2]; + if (re) begin + rd <= mem[ra]; + if (we1 && wa1 == ra) + rd <= wd1; + if (we2 && wa2 == ra) + rd[3:2] <= wd2[3:2]; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=2'b11 r:RD_COLLISION_X_MASK=2'b00 %i %i + +design -reset + +# Good case 13: wide read, narrow write. + +read_verilog << EOT + +module top( + input [7:0] addr, + input [7:0] wd, + input we, + input re, + input clk, + output reg [31:0] rd, +); + +reg [7:0] mem[0:255]; + +always @(posedge clk) begin + if (we) + mem[addr] <= wd; + if (re) begin + rd[7:0] <= mem[{addr[7:2], 2'b00}]; + rd[15:8] <= mem[{addr[7:2], 2'b01}]; + rd[23:16] <= mem[{addr[7:2], 2'b10}]; + rd[31:24] <= mem[{addr[7:2], 2'b11}]; + case ({we, addr[1:0]}) + 3'b100: rd[7:0] <= wd; + 3'b101: rd[15:8] <= wd; + 3'b110: rd[23:16] <= wd; + 3'b111: rd[31:24] <= wd; + endcase + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +dump +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i +memory_share +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i +select -assert-count 1 t:$mem_v2 r:RD_WIDE_CONTINUATION=4'b1110 %i + +design -reset + +# Good case 14: narrow read, wide write. + +read_verilog << EOT + +module top( + input [7:0] addr, + input [31:0] wd, + input we, + input re, + input clk, + output reg [7:0] rd, +); + +reg [7:0] mem[0:255]; + +always @(posedge clk) begin + if (we) begin + mem[{addr[7:2], 2'b00}] <= wd[7:0]; + mem[{addr[7:2], 2'b01}] <= wd[15:8]; + mem[{addr[7:2], 2'b10}] <= wd[23:16]; + mem[{addr[7:2], 2'b11}] <= wd[31:24]; + end + if (re) begin + rd <= mem[addr]; + case ({we, addr[1:0]}) + 3'b100: rd <= wd[7:0]; + 3'b101: rd <= wd[15:8]; + 3'b110: rd <= wd[23:16]; + 3'b111: rd <= wd[31:24]; + endcase + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +dump +memory_dff +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i +memory_share +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:RD_TRANSPARENCY_MASK=4'b1111 r:RD_COLLISION_X_MASK=4'b0000 %i %i +select -assert-count 1 t:$mem_v2 r:WR_WIDE_CONTINUATION=4'b1110 %i + +design -reset + +# Good case 15: wide read, wide write. + +read_verilog << EOT + +module top( + input [7:0] addr, + input [31:0] wd, + input we, + input re, + input clk, + output reg [31:0] rd, +); + +reg [7:0] mem[0:255]; + +always @(posedge clk) begin + if (we) begin + mem[{addr[7:2], 2'b00}] <= wd[7:0]; + mem[{addr[7:2], 2'b01}] <= wd[15:8]; + mem[{addr[7:2], 2'b10}] <= wd[23:16]; + mem[{addr[7:2], 2'b11}] <= wd[31:24]; + end + if (re) begin + rd[7:0] <= mem[{addr[7:2], 2'b00}]; + rd[15:8] <= mem[{addr[7:2], 2'b01}]; + rd[23:16] <= mem[{addr[7:2], 2'b10}]; + rd[31:24] <= mem[{addr[7:2], 2'b11}]; + if (we) + rd <= wd; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_dff +opt_clean +dump +memory_dff +select -assert-count 4 t:$memrd_v2 +select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0001 r:COLLISION_X_MASK=4'b1110 %i %i +select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0010 r:COLLISION_X_MASK=4'b1101 %i %i +select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b0100 r:COLLISION_X_MASK=4'b1011 %i %i +select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=4'b1000 r:COLLISION_X_MASK=4'b0111 %i %i +memory_share +select -assert-count 1 t:$memrd_v2 +select -assert-count 1 t:$memwr_v2 +select -assert-count 1 t:$memrd_v2 r:TRANSPARENCY_MASK=1'b1 r:COLLISION_X_MASK=1'b0 %i %i + +design -reset diff --git a/tests/opt/memory_map_offset.ys b/tests/opt/memory_map_offset.ys new file mode 100644 index 000000000..06969922d --- /dev/null +++ b/tests/opt/memory_map_offset.ys @@ -0,0 +1,100 @@ +read_verilog << EOT + +module top(...); + +input [3:0] ra; +input [3:0] wa; + +input [15:0] wd; +output [15:0] rd; +input en, clk; + +reg [15:0] mem[3:9]; + +always @(posedge clk) + if (en) + mem[wa] <= wd; + +assign rd = mem[ra]; + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_clean +memory_map + +design -stash gate + +read_verilog << EOT + +module top(...); + +input [3:0] ra; +input [3:0] wa; + +input [15:0] wd; +output reg [15:0] rd; +input en, clk; + +reg [15:0] \mem[3] ; +reg [15:0] \mem[4] ; +reg [15:0] \mem[5] ; +reg [15:0] \mem[6] ; +reg [15:0] \mem[7] ; +reg [15:0] \mem[8] ; +reg [15:0] \mem[9] ; + +always @(posedge clk) begin + if (en && wa == 3) + \mem[3] <= wd; + if (en && wa == 4) + \mem[4] <= wd; + if (en && wa == 5) + \mem[5] <= wd; + if (en && wa == 6) + \mem[6] <= wd; + if (en && wa == 7) + \mem[7] <= wd; + if (en && wa == 8) + \mem[8] <= wd; + if (en && wa == 9) + \mem[9] <= wd; +end + +always @* begin + rd = 16'bx; + if (ra == 3) + rd = \mem[3] ; + if (ra == 4) + rd = \mem[4] ; + if (ra == 5) + rd = \mem[5] ; + if (ra == 6) + rd = \mem[6] ; + if (ra == 7) + rd = \mem[7] ; + if (ra == 8) + rd = \mem[8] ; + if (ra == 9) + rd = \mem[9] ; +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_clean + +design -stash gold + +design -copy-from gold -as gold A:top +design -copy-from gate -as gate A:top + +equiv_make gold gate equiv +equiv_induct -undef equiv +equiv_status -assert equiv diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys index 0d567608d..7933f3e17 100644 --- a/tests/opt/opt_clean_init.ys +++ b/tests/opt/opt_clean_init.ys @@ -1,13 +1,22 @@ -logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1 -logger -expect-no-warnings -read_verilog <<EOT -module top; -(* init=1'b0 *) wire w = 1'b0; -(* init=1'bx *) wire x = 1'b0; -(* init=1'b1 *) wire y = 1'b0; -(* init=1'b0 *) wire z = 1'bx; +read_verilog << EOT +module top(...); + +input [1:0] D; +input C; +output O; +reg [1:0] Q; + +initial Q = 0; + +always @(posedge C) + Q <= D; + +assign O = Q[1]; + endmodule EOT -clean -select -assert-count 1 a:init -select -assert-count 1 w:y a:init %i + +synth +check -assert -initdrv + +select -assert-count 1 a:init=2'b0x diff --git a/tests/opt/opt_clean_mem.ys b/tests/opt/opt_clean_mem.ys index b35b15871..71f9e0d7b 100644 --- a/tests/opt/opt_clean_mem.ys +++ b/tests/opt/opt_clean_mem.ys @@ -22,28 +22,27 @@ endmodule EOT proc -memory_dff select -assert-count 2 t:$memrd -select -assert-count 1 t:$memwr -select -assert-count 1 t:$meminit +select -assert-count 1 t:$memwr_v2 +select -assert-count 1 t:$meminit_v2 design -save orig opt_clean select -assert-none t:$memrd -select -assert-none t:$memwr -select -assert-none t:$meminit +select -assert-none t:$memwr_v2 +select -assert-none t:$meminit_v2 design -load orig expose top/rd1 opt_clean select -assert-count 1 t:$memrd -select -assert-count 1 t:$memwr -select -assert-count 1 t:$meminit +select -assert-count 1 t:$memwr_v2 +select -assert-count 1 t:$meminit_v2 design -load orig expose top/rd1 top/rd2 opt_clean select -assert-count 2 t:$memrd -select -assert-count 1 t:$memwr -select -assert-count 1 t:$meminit +select -assert-count 1 t:$memwr_v2 +select -assert-count 1 t:$meminit_v2 diff --git a/tests/opt/opt_dff_sr.ys b/tests/opt/opt_dff_sr.ys index daedb115c..0961cb11e 100644 --- a/tests/opt/opt_dff_sr.ys +++ b/tests/opt/opt_dff_sr.ys @@ -22,8 +22,10 @@ EOT design -save orig -equiv_opt -undef -assert -multiclock opt_dff -design -load postopt +# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack. +#equiv_opt -undef -assert -multiclock opt_dff +#design -load postopt +opt_dff select -assert-count 1 t:$dffsr select -assert-count 1 t:$dffsr r:WIDTH=2 %i select -assert-count 1 t:$dffsre @@ -34,8 +36,9 @@ select -assert-none t:$sr design -load orig -equiv_opt -undef -assert -multiclock opt_dff -keepdc -design -load postopt +#equiv_opt -undef -assert -multiclock opt_dff -keepdc +#design -load postopt +opt_dff -keepdc select -assert-count 1 t:$dffsr select -assert-count 1 t:$dffsr r:WIDTH=4 %i select -assert-count 1 t:$dffsre @@ -48,8 +51,9 @@ select -assert-count 1 t:$sr r:WIDTH=4 %i design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -design -load postopt +#equiv_opt -undef -assert -multiclock opt_dff +#design -load postopt +opt_dff select -assert-count 1 t:$_DFF_PP0_ select -assert-count 1 t:$_DFF_PP1_ select -assert-count 1 t:$_DFFE_PN0P_ @@ -61,8 +65,9 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_ design -load orig simplemap -equiv_opt -undef -assert -multiclock opt_dff -keepdc -design -load postopt +#equiv_opt -undef -assert -multiclock opt_dff -keepdc +#design -load postopt +opt_dff -keepdc select -assert-count 1 t:$_DFF_PP0_ select -assert-count 1 t:$_DFF_PP1_ select -assert-count 2 t:$_DFFSR_PPP_ diff --git a/tests/opt/opt_expr_constconn.v b/tests/opt/opt_expr_constconn.v new file mode 100644 index 000000000..d18b120e3 --- /dev/null +++ b/tests/opt/opt_expr_constconn.v @@ -0,0 +1,8 @@ +module top(...); + +input [7:0] A; +output [7:0] B; +wire [7:0] C = 3; +assign B = A + C; + +endmodule diff --git a/tests/opt/opt_expr_constconn.ys b/tests/opt/opt_expr_constconn.ys new file mode 100644 index 000000000..9dd848a4b --- /dev/null +++ b/tests/opt/opt_expr_constconn.ys @@ -0,0 +1,7 @@ +read_verilog opt_expr_constconn.v +select -assert-count 1 t:$add +select -assert-count 1 t:$add %ci w:C %i +equiv_opt -assert opt_expr +design -load postopt +select -assert-count 1 t:$add +select -assert-count 0 t:$add %ci w:C %i diff --git a/tests/opt/opt_mem_feedback.ys b/tests/opt/opt_mem_feedback.ys new file mode 100644 index 000000000..06d6e7e77 --- /dev/null +++ b/tests/opt/opt_mem_feedback.ys @@ -0,0 +1,189 @@ +# Good case: proper feedback port. + +read_verilog << EOT + +module top(...); + +input clk; +input en; +input s; + +input [3:0] ra; +output [15:0] rd; +input [3:0] wa; +input [15:0] wd; + +reg [15:0] mem[0:15]; + +assign rd = mem[ra]; + +always @(posedge clk) begin + if (en) begin + mem[wa] <= {mem[wa][15:8], s ? wd[7:0] : mem[wa][7:0]}; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_clean + +design -save start +memory_map +design -save preopt + +design -load start +opt_mem_feedback +select -assert-count 1 t:$memrd_v2 +memory_map +design -save postopt + +equiv_opt -assert -run prepare: : + + + +design -reset + +# Bad case: read port also used for other things. + +read_verilog << EOT + +module top(...); + +input clk; +input en; +input s; + +output [15:0] rd; +input [3:0] wa; +input [15:0] wd; + +reg [15:0] mem[0:15]; + +assign rd = mem[wa]; + +always @(posedge clk) begin + if (en) begin + mem[wa] <= {s ? rd : wd[15:8], s ? wd[7:0] : rd}; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_clean + +design -save start +memory_map +design -save preopt + +design -load start +select -assert-count 1 t:$memrd +opt_mem_feedback +select -assert-count 1 t:$memrd +memory_map +design -save postopt + +equiv_opt -assert -run prepare: : + + + +design -reset + +# Bad case: another user of the mux out. + +read_verilog << EOT + +module top(...); + +input clk; +input en; +input s; + +output [15:0] rd; +input [3:0] wa; +input [15:0] wd; + +reg [15:0] mem[0:15]; + +assign rd = s ? wd : mem[wa]; + +always @(posedge clk) begin + if (en) begin + mem[wa] <= rd; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_clean + +design -save start +memory_map +design -save preopt + +design -load start +select -assert-count 1 t:$memrd +opt_mem_feedback +select -assert-count 1 t:$memrd +memory_map +design -save postopt + +equiv_opt -assert -run prepare: : + + + +design -reset + +# Tricky case: legit feedback path, but priority needs to be preserved. + +read_verilog << EOT + +module top(...); + +input clk; +input sel; +input [3:0] wa1; +input [3:0] wa2; +input [15:0] wd1; +input [3:0] ra; +output [15:0] rd; + +reg [15:0] mem [0:15]; + +always @(posedge clk) begin + mem[wa1] <= sel ? wd1 : mem[wa1]; + mem[wa2] <= mem[wa2]; +end + +assign rd = mem[ra]; + +endmodule + +EOT + +hierarchy -auto-top +proc +opt_clean + +design -save start +memory_map +design -save preopt + +design -load start +opt_mem_feedback +select -assert-count 1 t:$memrd_v2 +memory_map +design -save postopt + +equiv_opt -assert -run prepare: : diff --git a/tests/opt/opt_mem_priority.ys b/tests/opt/opt_mem_priority.ys new file mode 100644 index 000000000..a4119e12a --- /dev/null +++ b/tests/opt/opt_mem_priority.ys @@ -0,0 +1,209 @@ +# Bad case: independent write ports. + +read_verilog << EOT + +module top( + input [3:0] wa1, wa2, ra, wd1, wd2, + input clk, we1, we2, + output [3:0] rd); + +reg [3:0] mem[0:15]; +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2) + mem[wa2] <= wd2; +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt +memory -nomap +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0100 %i + + +design -reset + +# Good case: write ports with definitely different addresses. + +read_verilog << EOT + +module top( + input [3:0] wa, ra, wd1, wd2, + input clk, we1, we2, + output [3:0] rd); + +reg [3:0] mem[0:15]; +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) + mem[wa] <= wd1; + if (we2) + mem[wa ^ 1] <= wd2; +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt +memory -nomap +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i + + +design -reset + +# Bad case 2: the above, but broken. + +read_verilog << EOT + +module top( + input [3:0] wa, ra, wd1, wd2, + input clk, we1, we2, + output [3:0] rd); + +reg [3:0] mem[0:15]; +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) + mem[wa] <= wd1; + if (we2) + mem[wa | 1] <= wd2; +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt +memory -nomap +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0100 %i + + +design -reset + +# Good case 2: write ports with disjoint bit enables. + +read_verilog << EOT + +module top( + input [3:0] wa1, wa2, ra, + input [1:0] wd1, wd2, + input clk, we1, we2, + output [3:0] rd); + +reg [3:0] mem[0:15]; +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) + mem[wa1][1:0] <= wd1; + if (we2) + mem[wa2][3:2] <= wd2; +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt +memory -nomap +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i + + +design -reset + +# Good case 3: write ports with soft priority logic already + +read_verilog << EOT + +module top( + input [3:0] wa1, wa2, ra, wd1, wd2, + input clk, we1, we2, + output [3:0] rd); + +reg [3:0] mem[0:15]; +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) + mem[wa1] <= wd1; + if (we2 && wa1 != wa2) + mem[wa2] <= wd2; +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt +memory -nomap +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=4'b0000 %i + + +design -reset + +# Good case 4: two wide write ports + +read_verilog << EOT + +module top( + input [5:0] wa1, wa2, + input [7:0] ra, + input [31:0] wd1, wd2, + input clk, we1, we2, + output [7:0] rd); + +reg [7:0] mem[0:255]; +assign rd = mem[ra]; + +always @(posedge clk) begin + if (we1) begin + mem[{wa1, 2'b00}] <= wd1[7:0]; + mem[{wa1, 2'b01}] <= wd1[15:8]; + mem[{wa1, 2'b10}] <= wd1[23:16]; + mem[{wa1, 2'b11}] <= wd1[31:24]; + end + if (we2) begin + mem[{wa2, 2'b00}] <= wd2[7:0]; + mem[{wa2, 2'b01}] <= wd2[15:8]; + mem[{wa2, 2'b10}] <= wd2[23:16]; + mem[{wa2, 2'b11}] <= wd2[31:24]; + end +end + +endmodule + +EOT + +hierarchy -auto-top +proc +opt +opt_mem_priority +memory_collect +select -assert-count 1 t:$mem_v2 +select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0804020100000000 %i +memory_share +select -assert-count 1 t:$mem_v2 r:WR_PRIORITY_MASK=64'h0f0f0f0f00000000 %i +select -assert-count 1 t:$mem_v2 r:WR_WIDE_CONTINUATION=8'hee %i diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys index 0176f09c7..20b6cabee 100644 --- a/tests/opt/opt_merge_init.ys +++ b/tests/opt/opt_merge_init.ys @@ -48,7 +48,7 @@ EOT opt_merge select -assert-count 1 t:$dff -select -assert-count 1 a:init=2'bx1 +select -assert-count 1 a:init=2'bx1 a:init=2'b1x design -reset diff --git a/tests/opt/opt_reduce_bmux.ys b/tests/opt/opt_reduce_bmux.ys new file mode 100644 index 000000000..55e0b6d4b --- /dev/null +++ b/tests/opt/opt_reduce_bmux.ys @@ -0,0 +1,117 @@ +read_ilang << EOT + +module \top + wire width 12 input 0 \A + wire width 2 input 1 \S + wire width 6 output 2 \Y + + cell $bmux $0 + parameter \WIDTH 6 + parameter \S_WIDTH 2 + connect \A { \A [11:10] \A [3:2] \A [10:9] \A [7] \A [7] \A [8] \A [2] \A [7:6] \A [5] \A [5] \A [3:2] \A [5:4] \A [1] \A [1] \A [3:0] } + connect \S \S + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 1 t:$bmux r:WIDTH=4 %i + +design -reset + +read_ilang << EOT + +module \top + wire width 6 input 0 \A + wire width 2 input 1 \S + wire width 6 output 2 \Y + + cell $bmux $0 + parameter \WIDTH 6 + parameter \S_WIDTH 2 + connect \A { \A [5:0] \A [5:0] \A [5:0] \A [5:0] } + connect \S \S + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 0 t:$bmux + +design -reset + +read_ilang << EOT + +module \top + wire width 160 input 0 \A + wire width 2 input 1 \S + wire width 5 output 2 \Y + + cell $bmux $0 + parameter \WIDTH 5 + parameter \S_WIDTH 5 + connect \A \A + connect \S { \S [1] 1'1 \S [0] \S [1] 1'0 } + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 1 t:$bmux r:S_WIDTH=2 %i + +design -reset + +read_ilang << EOT + +module \top + wire width 10 input 0 \A + wire input 1 \S + wire width 5 output 2 \Y + + cell $bmux $0 + parameter \WIDTH 5 + parameter \S_WIDTH 1 + connect \A \A + connect \S \S + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 0 t:$bmux +select -assert-count 1 t:$mux + +design -reset + +read_ilang << EOT + +module \top + wire width 5 input 0 \A + wire width 5 output 1 \Y + + cell $bmux $0 + parameter \WIDTH 5 + parameter \S_WIDTH 0 + connect \A \A + connect \S { } + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 0 t:$bmux diff --git a/tests/opt/opt_reduce_demux.ys b/tests/opt/opt_reduce_demux.ys new file mode 100644 index 000000000..3c5bd7d43 --- /dev/null +++ b/tests/opt/opt_reduce_demux.ys @@ -0,0 +1,91 @@ +read_ilang << EOT + +module \top + wire width 4 input 0 \A + wire width 2 input 1 \S + wire width 24 output 2 \Y + + cell $demux $0 + parameter \WIDTH 6 + parameter \S_WIDTH 2 + connect \A { \A [3] \A [1] 1'0 \A [2:0] } + connect \S \S + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 1 t:$demux r:WIDTH=4 %i + +design -reset + +read_ilang << EOT + +module \top + wire width 2 input 1 \S + wire width 24 output 2 \Y + + cell $demux $0 + parameter \WIDTH 6 + parameter \S_WIDTH 2 + connect \A 6'000000 + connect \S \S + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 0 t:$demux + +design -reset + +read_ilang << EOT + +module \top + wire width 5 input 0 \A + wire width 2 input 1 \S + wire width 160 output 2 \Y + + cell $demux $0 + parameter \WIDTH 5 + parameter \S_WIDTH 5 + connect \A \A + connect \S { \S [0] \S [1] 1'1 \S [0] 1'0 } + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 1 t:$demux r:S_WIDTH=2 %i + +design -reset + +read_ilang << EOT + +module \top + wire width 5 input 0 \A + wire width 20 output 2 \Y + + cell $demux $0 + parameter \WIDTH 5 + parameter \S_WIDTH 2 + connect \A \A + connect \S { 2'10 } + connect \Y \Y + end +end + +EOT + +equiv_opt -assert opt_reduce -fine +opt_reduce -fine +select -assert-count 0 t:$demux diff --git a/tests/proc/bug2619.ys b/tests/proc/bug2619.ys new file mode 100644 index 000000000..a080b94f5 --- /dev/null +++ b/tests/proc/bug2619.ys @@ -0,0 +1,23 @@ +read_verilog << EOT + +module top(...); + +input D1, D2, R, CLK; +output reg Q1, Q2; + +always @(posedge CLK, posedge R) begin + Q1 <= 0; + if (!R) begin + Q1 <= D1; + Q2 <= D2; + end +end + +endmodule + +EOT + +proc +opt +select -assert-count 1 t:$adff +select -assert-count 1 t:$dffe diff --git a/tests/proc/bug2656.ys b/tests/proc/bug2656.ys new file mode 100644 index 000000000..3fe7cb33b --- /dev/null +++ b/tests/proc/bug2656.ys @@ -0,0 +1,31 @@ +read_verilog <<EOT +module top (...); + +input clk, rst, d1, d2; +output q1, q2; + +always @(posedge clk) + if (clk) + q1 <= d1; + +always @(posedge clk, posedge rst) + if (rst) + q2 <= 0; + else if (clk) + q2 <= d2; + +endmodule +EOT + +proc +opt + +select -assert-count 1 t:$dff +select -assert-count 1 w:clk %a %co t:$dff %i +select -assert-count 1 w:d1 %a %co t:$dff %i +select -assert-count 1 w:q1 %a %ci t:$dff %i +select -assert-count 1 t:$adff +select -assert-count 1 w:clk %a %co t:$adff %i +select -assert-count 1 w:rst %a %co t:$adff %i +select -assert-count 1 w:d2 %a %co t:$adff %i +select -assert-count 1 w:q2 %a %ci t:$adff %i diff --git a/tests/proc/bug2962.ys b/tests/proc/bug2962.ys new file mode 100644 index 000000000..99da8db5d --- /dev/null +++ b/tests/proc/bug2962.ys @@ -0,0 +1,22 @@ +read_ilang << EOT +module \top + wire width 4 input 1 \a + wire width 2 input 2 \b + wire input 3 \clk + wire width 4 output 4 \q + wire input 5 \en + wire width 4 \nq + process \p + assign \nq \a + assign \nq [1:0] \b + switch \en + case 1'1 + assign \nq [3] 1'0 + end + sync posedge \clk + update \q \nq + end +end +EOT +proc +check -assert diff --git a/tests/proc/rmdead.v b/tests/proc/rmdead.v new file mode 100644 index 000000000..2be89e533 --- /dev/null +++ b/tests/proc/rmdead.v @@ -0,0 +1,46 @@ +module top ( + input wire signed x, + output reg [31:0] y +); + wire signed fail = ~x; + + always @* + case (x) + 1'b0: y = 0; + 1'b1: y = 1; + default: y = fail; + endcase + + always @* + case (x) + 2'sb00: y = 0; + 2'sb00: y = fail; + endcase + + always @* + case (x) + 2'sb00: y = 0; + default: y = fail; + 2'sb01: y = 1; + 2'sb10: y = 2; + 2'sb11: y = 3; + 2'sb00: y = fail; + 2'sb01: y = fail; + 2'sb10: y = fail; + 2'sb11: y = fail; + endcase + + + always @* + case ({x, x}) + 2'b00: y = 0; + 2'b01: y = 1; + 2'b10: y = 2; + 2'b11: y = 3; + default: y = fail; + 2'b00: y = fail; + 2'b01: y = fail; + 2'b10: y = fail; + 2'b11: y = fail; + endcase +endmodule diff --git a/tests/proc/rmdead.ys b/tests/proc/rmdead.ys new file mode 100644 index 000000000..697d899e3 --- /dev/null +++ b/tests/proc/rmdead.ys @@ -0,0 +1,4 @@ +read_verilog rmdead.v +proc +opt_clean +select -assert-count 0 w:fail diff --git a/tests/sat/.gitignore b/tests/sat/.gitignore index 8355de9dc..664425d73 100644 --- a/tests/sat/.gitignore +++ b/tests/sat/.gitignore @@ -1,2 +1,4 @@ *.log run-test.mk +*.vcd +*.fst diff --git a/tests/sat/alu.v b/tests/sat/alu.v new file mode 100644 index 000000000..9826fe05d --- /dev/null +++ b/tests/sat/alu.v @@ -0,0 +1,79 @@ +module alu( + input clk, + input [7:0] A, + input [7:0] B, + input [3:0] operation, + output reg [7:0] result, + output reg CF, + output reg ZF, + output reg SF +); + + localparam ALU_OP_ADD /* verilator public_flat */ = 4'b0000; + localparam ALU_OP_SUB /* verilator public_flat */ = 4'b0001; + localparam ALU_OP_ADC /* verilator public_flat */ = 4'b0010; + localparam ALU_OP_SBC /* verilator public_flat */ = 4'b0011; + + localparam ALU_OP_AND /* verilator public_flat */ = 4'b0100; + localparam ALU_OP_OR /* verilator public_flat */ = 4'b0101; + localparam ALU_OP_NOT /* verilator public_flat */ = 4'b0110; + localparam ALU_OP_XOR /* verilator public_flat */ = 4'b0111; + + localparam ALU_OP_SHL /* verilator public_flat */ = 4'b1000; + localparam ALU_OP_SHR /* verilator public_flat */ = 4'b1001; + localparam ALU_OP_SAL /* verilator public_flat */ = 4'b1010; + localparam ALU_OP_SAR /* verilator public_flat */ = 4'b1011; + + localparam ALU_OP_ROL /* verilator public_flat */ = 4'b1100; + localparam ALU_OP_ROR /* verilator public_flat */ = 4'b1101; + localparam ALU_OP_RCL /* verilator public_flat */ = 4'b1110; + localparam ALU_OP_RCR /* verilator public_flat */ = 4'b1111; + + reg [8:0] tmp; + + always @(posedge clk) + begin + case (operation) + ALU_OP_ADD : + tmp = A + B; + ALU_OP_SUB : + tmp = A - B; + ALU_OP_ADC : + tmp = A + B + { 7'b0000000, CF }; + ALU_OP_SBC : + tmp = A - B - { 7'b0000000, CF }; + ALU_OP_AND : + tmp = {1'b0, A & B }; + ALU_OP_OR : + tmp = {1'b0, A | B }; + ALU_OP_NOT : + tmp = {1'b0, ~B }; + ALU_OP_XOR : + tmp = {1'b0, A ^ B}; + ALU_OP_SHL : + tmp = { A[7], A[6:0], 1'b0}; + ALU_OP_SHR : + tmp = { A[0], 1'b0, A[7:1]}; + ALU_OP_SAL : + // Same as SHL + tmp = { A[7], A[6:0], 1'b0}; + ALU_OP_SAR : + tmp = { A[0], A[7], A[7:1]}; + ALU_OP_ROL : + tmp = { A[7], A[6:0], A[7]}; + ALU_OP_ROR : + tmp = { A[0], A[0], A[7:1]}; + ALU_OP_RCL : + tmp = { A[7], A[6:0], CF}; + ALU_OP_RCR : + tmp = { A[0], CF, A[7:1]}; + endcase + + CF <= tmp[8]; + ZF <= tmp[7:0] == 0; + SF <= tmp[7]; + + result <= tmp[7:0]; + end +endmodule + diff --git a/tests/sat/grom.ys b/tests/sat/grom.ys new file mode 100644 index 000000000..da0f3b620 --- /dev/null +++ b/tests/sat/grom.ys @@ -0,0 +1,9 @@ +read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v; +prep -top grom_computer; +sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80 + +sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp + +sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold + +sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate diff --git a/tests/sat/grom_computer.v b/tests/sat/grom_computer.v new file mode 100644 index 000000000..63a5c8ff8 --- /dev/null +++ b/tests/sat/grom_computer.v @@ -0,0 +1,31 @@ +module grom_computer + (input clk, // Main Clock + input reset, // reset + output hlt, + output reg[7:0] display_out + ); + + wire [11:0] addr; + wire [7:0] memory_out; + wire [7:0] memory_in; + wire mem_enable; + wire we; + wire ioreq; + + grom_cpu cpu(.clk(clk),.reset(reset),.addr(addr),.data_in(memory_out),.data_out(memory_in),.we(we),.ioreq(ioreq),.hlt(hlt)); + + assign mem_enable = we & ~ioreq; + + ram_memory memory(.clk(clk),.addr(addr),.data_in(memory_in),.we(mem_enable),.data_out(memory_out)); + + always @(posedge clk) + begin + if(ioreq==1 && we==1) + begin + display_out <= memory_in; + `ifdef DISASSEMBLY + $display("Display output : %h", memory_in); + `endif + end + end +endmodule diff --git a/tests/sat/grom_cpu.v b/tests/sat/grom_cpu.v new file mode 100644 index 000000000..f9fef043b --- /dev/null +++ b/tests/sat/grom_cpu.v @@ -0,0 +1,747 @@ +module grom_cpu( + input clk, + input reset, + output reg [11:0] addr, + input [7:0] data_in, + output reg [7:0] data_out, + output reg we, + output reg ioreq, + output reg hlt +); + + reg[11:0] PC /* verilator public_flat */; // Program counter + reg[7:0] IR /* verilator public_flat */; // Instruction register + reg[7:0] VALUE /* verilator public_flat */; // Temp reg for storing 2nd operand + reg[3:0] CS /* verilator public_flat */; // Code segment regiser + reg[3:0] DS /* verilator public_flat */; // Data segment regiser + reg[11:0] SP /* verilator public_flat */; // Stack pointer regiser + reg[7:0] R[0:3] /* verilator public_flat */; // General purpose registers + reg[11:0] FUTURE_PC /* verilator public_flat */; // PC to jump to + + localparam STATE_RESET /*verilator public_flat*/ = 5'b00000; + localparam STATE_FETCH_PREP /*verilator public_flat*/ = 5'b00001; + localparam STATE_FETCH_WAIT /*verilator public_flat*/ = 5'b00010; + localparam STATE_FETCH /*verilator public_flat*/ = 5'b00011; + localparam STATE_EXECUTE /*verilator public_flat*/ = 5'b00100; + localparam STATE_FETCH_VALUE_PREP /*verilator public_flat*/ = 5'b00101; + localparam STATE_FETCH_VALUE /*verilator public_flat*/ = 5'b00110; + localparam STATE_EXECUTE_DBL /*verilator public_flat*/ = 5'b00111; + localparam STATE_LOAD_VALUE /*verilator public_flat*/ = 5'b01000; + localparam STATE_LOAD_VALUE_WAIT /*verilator public_flat*/ = 5'b01001; + localparam STATE_ALU_RESULT_WAIT /*verilator public_flat*/ = 5'b01010; + localparam STATE_ALU_RESULT /*verilator public_flat*/ = 5'b01011; + localparam STATE_PUSH_PC_LOW /*verilator public_flat*/ = 5'b01100; + localparam STATE_JUMP /*verilator public_flat*/ = 5'b01101; + localparam STATE_RET_VALUE_WAIT /*verilator public_flat*/ = 5'b01110; + localparam STATE_RET_VALUE /*verilator public_flat*/ = 5'b01111; + localparam STATE_RET_VALUE_WAIT2 /*verilator public_flat*/ = 5'b10000; + localparam STATE_RET_VALUE2 /*verilator public_flat*/ = 5'b10001; + + reg [4:0] state /* verilator public_flat */ = STATE_RESET; + + reg [7:0] alu_a /* verilator public_flat */; + reg [7:0] alu_b /* verilator public_flat */; + reg [3:0] alu_op /* verilator public_flat */; + + reg [1:0] RESULT_REG /* verilator public_flat */; + + wire [7:0] alu_res /* verilator public_flat */; + wire alu_CF /* verilator public_flat */; + wire alu_ZF /* verilator public_flat */; + wire alu_SF /* verilator public_flat */; + reg jump; + + alu alu(.clk(clk),.A(alu_a),.B(alu_b),.operation(alu_op),.result(alu_res),.CF(alu_CF),.ZF(alu_ZF),.SF(alu_SF)); + + always @(posedge clk) + begin + if (reset) + begin + state <= STATE_RESET; + hlt <= 0; + end + else + begin + case (state) + STATE_RESET : + begin + PC <= 12'h000; + state <= STATE_FETCH_PREP; + CS <= 4'h0; + DS <= 4'h0; + R[0] <= 8'h00; + R[1] <= 8'h00; + R[2] <= 8'h00; + R[3] <= 8'h00; + SP <= 12'hfff; + end + + STATE_FETCH_PREP : + begin + addr <= PC; + we <= 0; + ioreq <= 0; + + state <= STATE_FETCH_WAIT; + end + + STATE_FETCH_WAIT : + begin + // Sync with memory due to CLK + state <= (hlt) ? STATE_FETCH_PREP : STATE_FETCH; + end + + STATE_FETCH : + begin + IR <= data_in; + PC <= PC + 1; + + state <= STATE_EXECUTE; + end + STATE_EXECUTE : + begin + `ifdef DISASSEMBLY + $display(" PC %h R0 %h R1 %h R2 %h R3 %h CS %h DS %h SP %h ALU [%d %d %d]", PC, R[0], R[1], R[2], R[3], CS, DS, SP, alu_CF,alu_SF,alu_ZF); + `endif + if (IR[7]) + begin + addr <= PC; + state <= STATE_FETCH_VALUE_PREP; + PC <= PC + 1; + end + else + begin + case(IR[6:4]) + 3'b000 : + begin + `ifdef DISASSEMBLY + $display("MOV R%d,R%d",IR[3:2],IR[1:0]); + `endif + R[IR[3:2]] <= R[IR[1:0]]; + state <= STATE_FETCH_PREP; + end + 3'b001 : + begin + alu_a <= R[0]; // first input R0 + alu_b <= R[IR[1:0]]; + RESULT_REG <= 0; // result in R0 + alu_op <= { 2'b00, IR[3:2] }; + + state <= STATE_ALU_RESULT_WAIT; + + `ifdef DISASSEMBLY + case(IR[3:2]) + 2'b00 : begin + $display("ADD R%d",IR[1:0]); + end + 2'b01 : begin + $display("SUB R%d",IR[1:0]); + end + 2'b10 : begin + $display("ADC R%d",IR[1:0]); + end + 2'b11 : begin + $display("SBC R%d",IR[1:0]); + end + endcase + `endif + end + 3'b010 : + begin + alu_a <= R[0]; // first input R0 + alu_b <= R[IR[1:0]]; + RESULT_REG <= 0; // result in R0 + alu_op <= { 2'b01, IR[3:2] }; + state <= STATE_ALU_RESULT_WAIT; + `ifdef DISASSEMBLY + case(IR[3:2]) + 2'b00 : begin + $display("AND R%d",IR[1:0]); + end + 2'b01 : begin + $display("OR R%d",IR[1:0]); + end + 2'b10 : begin + $display("NOT R%d",IR[1:0]); + end + 2'b11 : begin + $display("XOR R%d",IR[1:0]); + end + endcase + `endif + end + 3'b011 : + begin + RESULT_REG <= IR[1:0]; // result in REG + // CMP and TEST are not storing result + state <= IR[3] ? STATE_FETCH_PREP : STATE_ALU_RESULT_WAIT; + // CMP and TEST are having first input R0, for INC and DEC is REG + alu_a <= IR[3] ? R[0] : R[IR[1:0]]; + // CMP and TEST are having second input REG, for INC and DEC is 1 + alu_b <= IR[3] ? R[IR[1:0]] : 8'b00000001; + + case(IR[3:2]) + 2'b00 : begin + `ifdef DISASSEMBLY + $display("INC R%d",IR[1:0]); + `endif + alu_op <= 4'b0001; // ALU_OP_ADD + end + 2'b01 : begin + `ifdef DISASSEMBLY + $display("DEC R%d",IR[1:0]); + `endif + alu_op <= 4'b0001; // ALU_OP_SUB + end + 2'b10 : begin + `ifdef DISASSEMBLY + $display("CMP R%d",IR[1:0]); + `endif + alu_op <= 4'b0001; // ALU_OP_SUB + end + 2'b11 : begin + `ifdef DISASSEMBLY + $display("TST R%d",IR[1:0]); + `endif + alu_op <= 4'b0100; // ALU_OP_AND + end + endcase + end + 3'b100 : + begin + if (IR[3]==0) + begin + alu_a <= R[0]; // first input R0 + // no 2nd input + RESULT_REG <= 0; // result in R0 + alu_op <= { 1'b1, IR[2:0] }; + `ifdef DISASSEMBLY + case(IR[2:0]) + 3'b000 : begin + $display("SHL"); + end + 3'b001 : begin + $display("SHR"); + end + 3'b010 : begin + $display("SAL"); + end + 3'b011 : begin + $display("SAR"); + end + 3'b100 : begin + $display("ROL"); + end + 3'b101 : begin + $display("ROR"); + end + 3'b110 : begin + $display("RCL"); + end + 3'b111 : begin + $display("RCR"); + end + endcase + `endif + state <= STATE_ALU_RESULT_WAIT; + end + else + begin + if (IR[2]==0) + begin + `ifdef DISASSEMBLY + $display("PUSH R%d",IR[1:0]); + `endif + addr <= SP; + we <= 1; + ioreq <= 0; + data_out <= R[IR[1:0]]; + SP <= SP - 1; + state <= STATE_FETCH_PREP; + end + else + begin + `ifdef DISASSEMBLY + $display("POP R%d",IR[1:0]); + `endif + addr <= SP + 1; + we <= 0; + ioreq <= 0; + RESULT_REG <= IR[1:0]; + SP <= SP + 1; + state <= STATE_LOAD_VALUE_WAIT; + end + end + end + 3'b101 : + begin + `ifdef DISASSEMBLY + $display("LOAD R%d,[R%d]", IR[3:2], IR[1:0]); + `endif + addr <= { DS, R[IR[1:0]] }; + we <= 0; + ioreq <= 0; + RESULT_REG <= IR[3:2]; + + state <= STATE_LOAD_VALUE_WAIT; + end + 3'b110 : + begin + `ifdef DISASSEMBLY + $display("STORE [R%d],R%d", IR[3:2], IR[1:0]); + `endif + addr <= { DS, R[IR[3:2]] }; + we <= 1; + ioreq <= 0; + data_out <= R[IR[1:0]]; + + state <= STATE_FETCH_PREP; + end + 3'b111 : + begin + // Special instuctions + case(IR[3:2]) + 2'b00 : begin + CS <= R[IR[1:0]][3:0]; + state <= STATE_FETCH_PREP; + `ifdef DISASSEMBLY + $display("MOV CS,R%d",IR[1:0]); + `endif + end + 2'b01 : begin + DS <= R[IR[1:0]][3:0]; + state <= STATE_FETCH_PREP; + `ifdef DISASSEMBLY + $display("MOV DS,R%d",IR[1:0]); + `endif + end + 2'b10 : begin + case(IR[1:0]) + 2'b00 : begin + `ifdef DISASSEMBLY + $display("PUSH CS"); + `endif + addr <= SP; + we <= 1; + ioreq <= 0; + data_out <= { 4'b0000, CS}; + SP <= SP - 1; + state <= STATE_FETCH_PREP; + end + 2'b01 : begin + `ifdef DISASSEMBLY + $display("PUSH DS"); + `endif + addr <= SP; + we <= 1; + ioreq <= 0; + data_out <= { 4'b0000, DS}; + SP <= SP - 1; + state <= STATE_FETCH_PREP; + end + 2'b10 : begin + `ifdef DISASSEMBLY + $display("Unused opcode"); + `endif + end + 2'b11 : begin + `ifdef DISASSEMBLY + $display("Unused opcode"); + `endif + end + endcase + state <= STATE_FETCH_PREP; + end + 2'b11 : begin + case(IR[1:0]) + 2'b00 : begin + `ifdef DISASSEMBLY + $display("Unused opcode"); + `endif + state <= STATE_FETCH_PREP; + end + 2'b01 : begin + `ifdef DISASSEMBLY + $display("Unused opcode"); + `endif + state <= STATE_FETCH_PREP; + end + 2'b10 : begin + `ifdef DISASSEMBLY + $display("RET"); + `endif + addr <= SP + 1; + we <= 0; + ioreq <= 0; + SP <= SP + 1; + state <= STATE_RET_VALUE_WAIT; + end + 2'b11 : begin + hlt <= 1; + `ifdef DISASSEMBLY + $display("HALT"); + `endif + state <= STATE_FETCH_PREP; + end + endcase + end + endcase + end + endcase + end + end + STATE_FETCH_VALUE_PREP : + begin + // Sync with memory due to CLK + state <= STATE_FETCH_VALUE; + end + STATE_FETCH_VALUE : + begin + VALUE <= data_in; + state <= STATE_EXECUTE_DBL; + end + STATE_EXECUTE_DBL : + begin + case(IR[6:4]) + 3'b000 : + begin + if (IR[3]==0) + begin + case(IR[2:0]) + 3'b000 : + begin + `ifdef DISASSEMBLY + $display("JMP %h ",{ CS, VALUE[7:0] }); + `endif + jump = 1; + end + 3'b001 : + begin + `ifdef DISASSEMBLY + $display("JC %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_CF==1); + end + 3'b010 : + begin + `ifdef DISASSEMBLY + $display("JNC %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_CF==0); + end + 3'b011 : + begin + `ifdef DISASSEMBLY + $display("JM %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_SF==1); + end + 3'b100 : + begin + `ifdef DISASSEMBLY + $display("JP %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_SF==0); + end + 3'b101 : + begin + `ifdef DISASSEMBLY + $display("JZ %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_ZF==1); + end + 3'b110 : + begin + `ifdef DISASSEMBLY + $display("JNZ %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_ZF==0); + end + 3'b111 : + begin + `ifdef DISASSEMBLY + $display("Unused opcode %h",IR); + `endif + jump = 0; + end + endcase + + if (jump) + begin + PC <= { CS, VALUE[7:0] }; + addr <= { CS, VALUE[7:0] }; + we <= 0; + ioreq <= 0; + end + state <= STATE_FETCH_PREP; + end + else + begin + case(IR[2:0]) + 3'b000 : + begin + `ifdef DISASSEMBLY + $display("JR %h ", PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]} ); + `endif + jump = 1; + end + 3'b001 : + begin + `ifdef DISASSEMBLY + $display("JRC %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_CF==1); + end + 3'b010 : + begin + `ifdef DISASSEMBLY + $display("JRNC %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_CF==0); + end + 3'b011 : + begin + `ifdef DISASSEMBLY + $display("JRM %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_SF==1); + end + 3'b100 : + begin + `ifdef DISASSEMBLY + $display("JRP %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_SF==0); + end + 3'b101 : + begin + `ifdef DISASSEMBLY + $display("JRZ %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_ZF==1); + end + 3'b110 : + begin + `ifdef DISASSEMBLY + $display("JRNZ %h ",{CS, VALUE[7:0] }); + `endif + jump = (alu_ZF==0); + end + 3'b111 : + begin + `ifdef DISASSEMBLY + $display("Unused opcode %h",IR); + `endif + jump = 0; + end + endcase + if (jump) + begin + PC <= PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]}; + addr <= PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]}; + we <= 0; + ioreq <= 0; + end + state <= STATE_FETCH_PREP; + end + end + 3'b001 : + begin + `ifdef DISASSEMBLY + $display("JUMP %h ",{ IR[3:0], VALUE[7:0] }); + `endif + PC <= { IR[3:0], VALUE[7:0] }; + addr <= { IR[3:0], VALUE[7:0] }; + we <= 0; + ioreq <= 0; + state <= STATE_FETCH_PREP; + end + 3'b010 : + begin + `ifdef DISASSEMBLY + $display("CALL %h ",{ IR[3:0], VALUE[7:0] }); + `endif + FUTURE_PC <= { IR[3:0], VALUE[7:0] }; + addr <= SP; + we <= 1; + ioreq <= 0; + data_out <= { 4'b0000, PC[11:8]}; + SP <= SP - 1; + state <= STATE_PUSH_PC_LOW; + end + 3'b011 : + begin + `ifdef DISASSEMBLY + $display("MOV SP,%h ",{ IR[3:0], VALUE[7:0] }); + `endif + SP <= { IR[3:0], VALUE[7:0] }; + state <= STATE_FETCH_PREP; + end + 3'b100 : + begin + `ifdef DISASSEMBLY + $display("IN R%d,[0x%h]",IR[1:0], VALUE); + `endif + ioreq <= 1; + we <= 0; + addr <= { 4'b0000, VALUE }; + RESULT_REG <= IR[1:0]; + state <= STATE_LOAD_VALUE_WAIT; + end + 3'b101 : + begin + `ifdef DISASSEMBLY + $display("OUT [0x%h],R%d",VALUE,IR[1:0]); + `endif + ioreq <= 1; + we <= 1; + addr <= { 4'b0000, VALUE }; + data_out <= R[IR[1:0]]; + state <= STATE_FETCH_PREP; + end + 3'b110 : + begin + // Special instuctions + case(IR[1:0]) + 2'b00 : begin + `ifdef DISASSEMBLY + $display("MOV CS,0x%h",VALUE); + `endif + CS <= VALUE[3:0]; + state <= STATE_FETCH_PREP; + end + 2'b01 : begin + `ifdef DISASSEMBLY + $display("MOV DS,0x%h",VALUE); + `endif + DS <= VALUE[3:0]; + state <= STATE_FETCH_PREP; + end + 2'b10 : begin + `ifdef DISASSEMBLY + $display("Unused opcode %h",IR); + `endif + state <= STATE_FETCH_PREP; + end + 2'b11 : begin + `ifdef DISASSEMBLY + $display("Unused opcode %h",IR); + `endif + state <= STATE_FETCH_PREP; + end + endcase + end + 3'b111 : + begin + case(IR[3:2]) + 2'b00 : begin + `ifdef DISASSEMBLY + $display("MOV R%d,0x%h",IR[1:0],VALUE); + `endif + R[IR[1:0]] <= VALUE; + state <= STATE_FETCH_PREP; + end + 2'b01 : begin + `ifdef DISASSEMBLY + $display("LOAD R%d,[0x%h]",IR[1:0], {DS, VALUE}); + `endif + addr <= { DS, VALUE }; + we <= 0; + ioreq <= 0; + RESULT_REG <= IR[1:0]; + + state <= STATE_LOAD_VALUE_WAIT; + end + 2'b10 : begin + `ifdef DISASSEMBLY + $display("STORE [0x%h],R%d", {DS, VALUE}, IR[1:0]); + `endif + addr <= { DS, VALUE }; + we <= 1; + ioreq <= 0; + data_out <= R[IR[1:0]]; + + state <= STATE_FETCH_PREP; + end + 2'b11 : begin + `ifdef DISASSEMBLY + $display("Unused opcode %h",IR); + `endif + state <= STATE_FETCH_PREP; + end + endcase + end + endcase + end + STATE_LOAD_VALUE_WAIT : + begin + // Sync with memory due to CLK + state <= STATE_LOAD_VALUE; + end + STATE_LOAD_VALUE : + begin + R[RESULT_REG] <= data_in; + we <= 0; + state <= STATE_FETCH_PREP; + end + STATE_ALU_RESULT_WAIT : + begin + state <= STATE_ALU_RESULT; + end + STATE_ALU_RESULT : + begin + R[RESULT_REG] <= alu_res; + state <= STATE_FETCH_PREP; + end + STATE_PUSH_PC_LOW : + begin + addr <= SP; + we <= 1; + ioreq <= 0; + data_out <= PC[7:0]; + SP <= SP - 1; + state <= STATE_JUMP; + end + STATE_JUMP : + begin + `ifdef DISASSEMBLY + $display("Jumping to %h",FUTURE_PC); + `endif + PC <= FUTURE_PC; + state <= STATE_FETCH_PREP; + end + STATE_RET_VALUE_WAIT : + begin + // Sync with memory due to CLK + state <= STATE_RET_VALUE; + end + STATE_RET_VALUE : + begin + FUTURE_PC <= { 4'b0000, data_in }; + we <= 0; + state <= STATE_RET_VALUE_WAIT2; + + addr <= SP + 1; + we <= 0; + ioreq <= 0; + SP <= SP + 1; + end + STATE_RET_VALUE_WAIT2 : + begin + // Sync with memory due to CLK + state <= STATE_RET_VALUE2; + end + STATE_RET_VALUE2 : + begin + FUTURE_PC <= FUTURE_PC | ({ 4'b0000, data_in } << 8); + we <= 0; + state <= STATE_JUMP; + end + default : + begin + state <= STATE_FETCH_PREP; + end + endcase + end + end +endmodule diff --git a/tests/sat/ram_memory.v b/tests/sat/ram_memory.v new file mode 100644 index 000000000..053ef206c --- /dev/null +++ b/tests/sat/ram_memory.v @@ -0,0 +1,37 @@ +module ram_memory( + input clk, + input [11:0] addr, + input [7:0] data_in, + input we, + output reg [7:0] data_out +); + + reg [7:0] store[0:4095] /* verilator public_flat */; + + initial + begin + store[0] <= 8'b11100001; // MOV DS,2 + store[1] <= 8'b00000010; // + store[2] <= 8'b01010100; // LOAD R1,[R0] + store[3] <= 8'b00110001; // INC R1 + store[4] <= 8'b00110001; // INC R1 + store[5] <= 8'b01100001; // STORE [R0],R1 + store[6] <= 8'b11010001; // OUT [0],R1 + store[7] <= 8'b00000000; // + store[8] <= 8'b00110001; // INC R1 + store[9] <= 8'b10100001; // CALL 0x100 + store[10] <= 8'b00000000; // + store[11] <= 8'b01111111; // HLT + + + store[256] <= 8'b11010001; // OUT [0],R1 + store[257] <= 8'b00000000; // + store[258] <= 8'b01111110; // RET + end + + always @(posedge clk) + if (we) + store[addr] <= data_in; + else + data_out <= store[addr]; +endmodule diff --git a/tests/sat/sim_counter.ys b/tests/sat/sim_counter.ys new file mode 100644 index 000000000..a0ff41b6e --- /dev/null +++ b/tests/sat/sim_counter.ys @@ -0,0 +1,48 @@ +# Create stimulus file +read_verilog <<EOT +module top (clk, reset, cnt); + +input clk; +input reset; +output [7:0] cnt; + +reg [7:0] cnt; + +endmodule +EOT +prep -top top; +sim -clock clk -reset reset -fst stimulus.fst -n 10 +design -reset + +# Counter implementation +read_verilog <<EOT +module top (clk, reset, cnt); + +input clk; +input reset; +output [7:0] cnt; + +reg [7:0] cnt; + +always @(posedge clk) + if (!reset) + cnt = cnt + 1; + else + cnt = 0; + +endmodule +EOT +prep -top top; + +# Simulate with stimulus +sim -clock clk -scope top -r stimulus.fst + +# Stimulus does not have counter values +# x in FST can match any value in simulation +sim -clock clk -scope top -r stimulus.fst -sim-gate + +# Stimulus does not have counter values +# x in simulation can match any value in FST +# so we expect error +logger -expect error "Signal difference" 1 +sim -clock clk -scope top -r stimulus.fst -sim-gold diff --git a/tests/simple/asgn_binop.sv b/tests/simple/asgn_binop.sv new file mode 100644 index 000000000..b134e5697 --- /dev/null +++ b/tests/simple/asgn_binop.sv @@ -0,0 +1,23 @@ +`define TEST(name, asgnop)\ + module test_``name ( \ + input logic [3:0] a, b, \ + output logic [3:0] c \ + ); \ + always @* begin \ + c = a; \ + c asgnop b; \ + end \ + endmodule + +`TEST(add, +=) +`TEST(sub, -=) +`TEST(mul, *=) +`TEST(div, /=) +`TEST(mod, %=) +`TEST(bit_and, &=) +`TEST(bit_or , |=) +`TEST(bit_xor, ^=) +`TEST(shl, <<=) +`TEST(shr, >>=) +`TEST(sshl, <<<=) +`TEST(sshr, >>>=) diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v index adef34f5b..d6e36fb80 100644 --- a/tests/simple/attrib01_module.v +++ b/tests/simple/attrib01_module.v @@ -1,4 +1,4 @@ -module bar(clk, rst, inp, out); +module attrib01_bar(clk, rst, inp, out); input wire clk; input wire rst; input wire inp; @@ -10,12 +10,12 @@ module bar(clk, rst, inp, out); endmodule -module foo(clk, rst, inp, out); +module attrib01_foo(clk, rst, inp, out); input wire clk; input wire rst; input wire inp; output wire out; - bar bar_instance (clk, rst, inp, out); + attrib01_bar bar_instance (clk, rst, inp, out); endmodule diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v index 3505e7265..989213b77 100644 --- a/tests/simple/attrib02_port_decl.v +++ b/tests/simple/attrib02_port_decl.v @@ -1,4 +1,4 @@ -module bar(clk, rst, inp, out); +module attrib02_bar(clk, rst, inp, out); (* this_is_clock = 1 *) input wire clk; (* this_is_reset = 1 *) @@ -13,13 +13,13 @@ module bar(clk, rst, inp, out); endmodule -module foo(clk, rst, inp, out); +module attrib02_foo(clk, rst, inp, out); (* this_is_the_master_clock *) input wire clk; input wire rst; input wire inp; output wire out; - bar bar_instance (clk, rst, inp, out); + attrib02_bar bar_instance (clk, rst, inp, out); endmodule diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v index 562d225cd..d2ae98978 100644 --- a/tests/simple/attrib03_parameter.v +++ b/tests/simple/attrib03_parameter.v @@ -1,4 +1,4 @@ -module bar(clk, rst, inp, out); +module attrib03_bar(clk, rst, inp, out); (* bus_width *) parameter WIDTH = 2; @@ -17,12 +17,12 @@ module bar(clk, rst, inp, out); endmodule -module foo(clk, rst, inp, out); +module attrib03_foo(clk, rst, inp, out); input wire clk; input wire rst; input wire [7:0] inp; output wire [7:0] out; - bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out); + attrib03_bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out); endmodule diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v index 8b5523406..98826e971 100644 --- a/tests/simple/attrib04_net_var.v +++ b/tests/simple/attrib04_net_var.v @@ -1,4 +1,4 @@ -module bar(clk, rst, inp, out); +module attrib04_bar(clk, rst, inp, out); input wire clk; input wire rst; input wire inp; @@ -21,12 +21,12 @@ module bar(clk, rst, inp, out); endmodule -module foo(clk, rst, inp, out); +module attrib04_foo(clk, rst, inp, out); input wire clk; input wire rst; input wire inp; output wire out; - bar bar_instance (clk, rst, inp, out); + attrib04_bar bar_instance (clk, rst, inp, out); endmodule diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED index e20e66319..8cc471f4e 100644 --- a/tests/simple/attrib05_port_conn.v.DISABLED +++ b/tests/simple/attrib05_port_conn.v.DISABLED @@ -1,4 +1,4 @@ -module bar(clk, rst, inp, out); +module attrib05_bar(clk, rst, inp, out); input wire clk; input wire rst; input wire inp; @@ -10,12 +10,12 @@ module bar(clk, rst, inp, out); endmodule -module foo(clk, rst, inp, out); +module attrib05_foo(clk, rst, inp, out); input wire clk; input wire rst; input wire inp; output wire out; - bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); + attrib05_bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); endmodule diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v index e21173c58..2bc136f9a 100644 --- a/tests/simple/attrib06_operator_suffix.v +++ b/tests/simple/attrib06_operator_suffix.v @@ -1,4 +1,4 @@ -module bar(clk, rst, inp_a, inp_b, out); +module attrib06_bar(clk, rst, inp_a, inp_b, out); input wire clk; input wire rst; input wire [7:0] inp_a; @@ -11,13 +11,13 @@ module bar(clk, rst, inp_a, inp_b, out); endmodule -module foo(clk, rst, inp_a, inp_b, out); +module attrib06_foo(clk, rst, inp_a, inp_b, out); input wire clk; input wire rst; input wire [7:0] inp_a; input wire [7:0] inp_b; output wire [7:0] out; - bar bar_instance (clk, rst, inp_a, inp_b, out); + attrib06_bar bar_instance (clk, rst, inp_a, inp_b, out); endmodule diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED index f55ef2316..282fc5da7 100644 --- a/tests/simple/attrib07_func_call.v.DISABLED +++ b/tests/simple/attrib07_func_call.v.DISABLED @@ -1,4 +1,4 @@ -function [7:0] do_add; +function [7:0] attrib07_do_add; input [7:0] inp_a; input [7:0] inp_b; @@ -6,7 +6,7 @@ function [7:0] do_add; endfunction -module foo(clk, rst, inp_a, inp_b, out); +module attri07_foo(clk, rst, inp_a, inp_b, out); input wire clk; input wire rst; input wire [7:0] inp_a; @@ -15,7 +15,7 @@ module foo(clk, rst, inp_a, inp_b, out); always @(posedge clk) if (rst) out <= 0; - else out <= do_add (* combinational_adder *) (inp_a, inp_b); + else out <= attrib07_do_add (* combinational_adder *) (inp_a, inp_b); endmodule diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v index c5a32234e..759e67c7b 100644 --- a/tests/simple/attrib08_mod_inst.v +++ b/tests/simple/attrib08_mod_inst.v @@ -1,4 +1,4 @@ -module bar(clk, rst, inp, out); +module attrib08_bar(clk, rst, inp, out); input wire clk; input wire rst; input wire inp; @@ -10,13 +10,13 @@ module bar(clk, rst, inp, out); endmodule -module foo(clk, rst, inp, out); +module attrib08_foo(clk, rst, inp, out); input wire clk; input wire rst; input wire inp; output wire out; (* my_module_instance = 99 *) - bar bar_instance (clk, rst, inp, out); + attrib08_bar bar_instance (clk, rst, inp, out); endmodule diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v index 8551bf9d0..a72b81dda 100644 --- a/tests/simple/attrib09_case.v +++ b/tests/simple/attrib09_case.v @@ -1,4 +1,4 @@ -module bar(clk, rst, inp, out); +module attrib09_bar(clk, rst, inp, out); input wire clk; input wire rst; input wire [1:0] inp; @@ -15,12 +15,12 @@ module bar(clk, rst, inp, out); endmodule -module foo(clk, rst, inp, out); +module attrib09_foo(clk, rst, inp, out); input wire clk; input wire rst; input wire [1:0] inp; output wire [1:0] out; - bar bar_instance (clk, rst, inp, out); + attrib09_bar bar_instance (clk, rst, inp, out); endmodule diff --git a/tests/simple/case_expr_const.v b/tests/simple/case_expr_const.v new file mode 100644 index 000000000..d9169c084 --- /dev/null +++ b/tests/simple/case_expr_const.v @@ -0,0 +1,49 @@ +// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both +// the constant and non-constant case evaluation logic is covered +module case_expr_const_top( + // expected to output all 1s + output reg a, b, c, d, e, f, g, h +); + initial begin + case (2'b0) + 1'b0: a = 1; + default: a = 0; + endcase + case (2'sb11) + 2'sb01: b = 0; + 1'sb1: b = 1; + endcase + case (2'sb11) + 1'sb0: c = 0; + 1'sb1: c = 1; + endcase + case (2'sb11) + 1'b0: d = 0; + 1'sb1: d = 0; + default: d = 1; + endcase + case (2'b11) + 1'sb0: e = 0; + 1'sb1: e = 0; + default: e = 1; + endcase + case (1'sb1) + 1'sb0: f = 0; + 2'sb11: f = 1; + default: f = 0; + endcase + case (1'sb1) + 1'sb0: g = 0; + 3'b0: g = 0; + 2'sb11: g = 0; + default: g = 1; + endcase + case (1'sb1) + 1'sb0: h = 0; + 1'b1: h = 1; + 3'b0: h = 0; + 2'sb11: h = 0; + default: h = 0; + endcase + end +endmodule diff --git a/tests/simple/case_expr_extend.sv b/tests/simple/case_expr_extend.sv new file mode 100644 index 000000000..d4ca2aa9b --- /dev/null +++ b/tests/simple/case_expr_extend.sv @@ -0,0 +1,11 @@ +module top( + output logic [5:0] out +); +initial begin + out = '0; + case (1'b1 << 1) + 2'b10: out = '1; + default: out = '0; + endcase +end +endmodule diff --git a/tests/simple/case_expr_non_const.v b/tests/simple/case_expr_non_const.v new file mode 100644 index 000000000..6dfc2e54e --- /dev/null +++ b/tests/simple/case_expr_non_const.v @@ -0,0 +1,59 @@ +// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both +// the constant and non-constant case evaluation logic is covered +module case_expr_non_const_top( + // expected to output all 1s + output reg a, b, c, d, e, f, g, h +); + reg x_1b0 = 1'b0; + reg x_1b1 = 1'b1; + reg signed x_1sb0 = 1'sb0; + reg signed x_1sb1 = 1'sb1; + reg [1:0] x_2b0 = 2'b0; + reg [1:0] x_2b11 = 2'b11; + reg signed [1:0] x_2sb01 = 2'sb01; + reg signed [1:0] x_2sb11 = 2'sb11; + reg [2:0] x_3b0 = 3'b0; + + initial begin + case (x_2b0) + x_1b0: a = 1; + default: a = 0; + endcase + case (x_2sb11) + x_2sb01: b = 0; + x_1sb1: b = 1; + endcase + case (x_2sb11) + x_1sb0: c = 0; + x_1sb1: c = 1; + endcase + case (x_2sb11) + x_1b0: d = 0; + x_1sb1: d = 0; + default: d = 1; + endcase + case (x_2b11) + x_1sb0: e = 0; + x_1sb1: e = 0; + default: e = 1; + endcase + case (x_1sb1) + x_1sb0: f = 0; + x_2sb11: f = 1; + default: f = 0; + endcase + case (x_1sb1) + x_1sb0: g = 0; + x_3b0: g = 0; + x_2sb11: g = 0; + default: g = 1; + endcase + case (x_1sb1) + x_1sb0: h = 0; + x_1b1: h = 1; + x_3b0: h = 0; + x_2sb11: h = 0; + default: h = 0; + endcase + end +endmodule diff --git a/tests/simple/case_expr_query.sv b/tests/simple/case_expr_query.sv new file mode 100644 index 000000000..844dfb713 --- /dev/null +++ b/tests/simple/case_expr_query.sv @@ -0,0 +1,32 @@ +module top( + output logic [5:0] out +); +initial begin + out = '0; + case ($bits (out)) 6: + case ($size (out)) 6: + case ($high (out)) 5: + case ($low (out)) 0: + case ($left (out)) 5: + case ($right(out)) 0: + case (6) $bits (out): + case (6) $size (out): + case (5) $high (out): + case (0) $low (out): + case (5) $left (out): + case (0) $right(out): + out = '1; + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase + endcase +end +endmodule diff --git a/tests/simple/case_large.v b/tests/simple/case_large.v new file mode 100644 index 000000000..ec8ed6038 --- /dev/null +++ b/tests/simple/case_large.v @@ -0,0 +1,273 @@ +module case_lage_top ( + input wire [127:0] x, + output reg [31:0] y +); + localparam A = 32'hDEAD_BEEF; + localparam B = 32'h0BAD_0B01; + localparam C = 32'hC001_D00D; + localparam D = 32'h1234_5678; + + always @* + case (x) + + {C,A,D,B}: y = 142; + {C,A,D,A}: y = 141; + {D,D,A,A}: y = 241; + {A,C,C,D}: y = 44; + {A,A,A,C}: y = 3; + {A,B,A,C}: y = 19; + {A,D,C,C}: y = 59; + {A,A,C,C}: y = 11; + {D,C,B,B}: y = 230; + {A,A,D,D}: y = 16; + {A,C,A,A}: y = 33; + {A,D,D,D}: y = 64; + {D,B,C,B}: y = 218; + {A,C,B,D}: y = 40; + {C,A,B,B}: y = 134; + {A,C,C,C}: y = 43; + {D,A,D,D}: y = 208; + {A,B,C,A}: y = 25; + {B,A,B,B}: y = 70; + {A,C,B,B}: y = 38; + {C,C,C,B}: y = 170; + {C,D,A,C}: y = 179; + {B,C,D,B}: y = 110; + {A,D,A,C}: y = 51; + {C,C,B,B}: y = 166; + {D,D,D,B}: y = 254; + {C,A,D,C}: y = 143; + {C,D,D,B}: y = 190; + {C,B,A,A}: y = 145; + {C,B,A,C}: y = 147; + {B,C,C,B}: y = 106; + {C,D,C,A}: y = 185; + {C,D,B,D}: y = 184; + {D,D,D,D}: y = 256; + {D,C,C,C}: y = 235; + {D,C,D,B}: y = 238; + {A,B,D,C}: y = 31; + {A,C,A,D}: y = 36; + {C,B,C,B}: y = 154; + {A,B,A,A}: y = 17; + {C,B,B,A}: y = 149; + {B,B,D,C}: y = 95; + {B,D,C,B}: y = 122; + {D,B,A,A}: y = 209; + {B,A,B,A}: y = 69; + {B,A,D,A}: y = 77; + {A,B,B,B}: y = 22; + {C,C,C,C}: y = 171; + {C,A,C,B}: y = 138; + {B,A,D,D}: y = 80; + {C,D,D,C}: y = 191; + {B,A,A,C}: y = 67; + {D,C,D,C}: y = 239; + {C,D,D,D}: y = 192; + {C,D,B,B}: y = 182; + {B,B,A,C}: y = 83; + {D,A,A,D}: y = 196; + {A,C,C,B}: y = 42; + {B,C,A,A}: y = 97; + {A,D,B,A}: y = 53; + {D,D,B,C}: y = 247; + {A,A,C,A}: y = 9; + {D,A,C,B}: y = 202; + {A,C,B,C}: y = 39; + {B,C,B,A}: y = 101; + {B,B,B,C}: y = 87; + {C,B,A,B}: y = 146; + {B,D,A,D}: y = 116; + {A,B,D,D}: y = 32; + {B,A,B,C}: y = 71; + {C,A,A,A}: y = 129; + {B,A,D,C}: y = 79; + {B,A,C,B}: y = 74; + {B,B,D,B}: y = 94; + {B,B,C,C}: y = 91; + {D,C,C,A}: y = 233; + {C,A,B,A}: y = 133; + {D,A,B,A}: y = 197; + {D,B,B,D}: y = 216; + {C,C,A,C}: y = 163; + {D,D,B,A}: y = 245; + {B,A,D,B}: y = 78; + {A,B,C,D}: y = 28; + {C,C,C,D}: y = 172; + {D,C,A,D}: y = 228; + {A,C,D,A}: y = 45; + {B,D,C,C}: y = 123; + {C,B,A,D}: y = 148; + {B,D,B,B}: y = 118; + {A,D,A,B}: y = 50; + {C,B,B,C}: y = 151; + {A,A,A,A}: y = 1; + {A,A,B,B}: y = 6; + {B,B,B,B}: y = 86; + {A,D,A,A}: y = 49; + {A,A,A,B}: y = 2; + {B,D,D,A}: y = 125; + {C,C,D,B}: y = 174; + {D,A,D,B}: y = 206; + {D,D,B,D}: y = 248; + {A,A,A,D}: y = 4; + {B,A,A,B}: y = 66; + {B,C,C,A}: y = 105; + {B,C,C,C}: y = 107; + {D,D,D,C}: y = 255; + {B,C,D,D}: y = 112; + {A,D,B,C}: y = 55; + {C,C,C,A}: y = 169; + {C,D,B,C}: y = 183; + {A,A,B,D}: y = 8; + {D,C,B,A}: y = 229; + {C,B,D,A}: y = 157; + {A,D,D,C}: y = 63; + {D,A,D,A}: y = 205; + {A,A,B,C}: y = 7; + {A,C,A,B}: y = 34; + {C,B,D,C}: y = 159; + {C,C,D,D}: y = 176; + {D,D,D,A}: y = 253; + {A,B,B,D}: y = 24; + {B,B,C,A}: y = 89; + {B,D,C,A}: y = 121; + {A,B,C,C}: y = 27; + {A,A,D,C}: y = 15; + {A,B,B,A}: y = 21; + {A,D,A,D}: y = 52; + {D,D,C,C}: y = 251; + {C,D,A,B}: y = 178; + {A,A,D,B}: y = 14; + {D,B,D,B}: y = 222; + {A,C,C,A}: y = 41; + {D,D,A,C}: y = 243; + {A,C,D,B}: y = 46; + {B,B,B,D}: y = 88; + {D,B,B,B}: y = 214; + {C,C,B,D}: y = 168; + {A,D,D,A}: y = 61; + {D,A,C,C}: y = 203; + {D,C,A,C}: y = 227; + {C,D,C,D}: y = 188; + {D,B,D,D}: y = 224; + {A,C,D,C}: y = 47; + {B,A,B,D}: y = 72; + {A,B,B,C}: y = 23; + {C,C,D,A}: y = 173; + {D,B,C,C}: y = 219; + {D,B,C,A}: y = 217; + {A,D,C,D}: y = 60; + {B,B,D,A}: y = 93; + {A,D,C,A}: y = 57; + {C,C,A,A}: y = 161; + {C,B,B,D}: y = 152; + {B,B,B,A}: y = 85; + {B,D,A,A}: y = 113; + {D,C,D,A}: y = 237; + {B,C,B,C}: y = 103; + {A,B,C,B}: y = 26; + {C,D,A,D}: y = 180; + {A,D,B,D}: y = 56; + {D,C,A,B}: y = 226; + {D,B,B,C}: y = 215; + {D,A,B,C}: y = 199; + {B,D,A,C}: y = 115; + {C,B,C,D}: y = 156; + {B,D,D,B}: y = 126; + {D,D,C,B}: y = 250; + {D,C,C,D}: y = 236; + {B,C,B,D}: y = 104; + {C,B,C,A}: y = 153; + {C,B,B,B}: y = 150; + {C,D,C,B}: y = 186; + {C,D,C,C}: y = 187; + {A,D,B,B}: y = 54; + {D,C,C,B}: y = 234; + {C,B,D,D}: y = 160; + {A,B,A,D}: y = 20; + {C,C,B,A}: y = 165; + {C,D,D,A}: y = 189; + {C,C,D,C}: y = 175; + {D,B,D,C}: y = 223; + {B,C,A,B}: y = 98; + {C,C,A,B}: y = 162; + {B,C,D,A}: y = 109; + {D,A,B,D}: y = 200; + {B,D,C,D}: y = 124; + {D,D,C,A}: y = 249; + {B,A,C,C}: y = 75; + {A,A,C,B}: y = 10; + {C,A,B,D}: y = 136; + {B,B,C,D}: y = 92; + {D,D,C,D}: y = 252; + {B,C,A,D}: y = 100; + {C,A,C,C}: y = 139; + {C,A,C,D}: y = 140; + {D,C,A,A}: y = 225; + {A,D,C,B}: y = 58; + {D,B,C,D}: y = 220; + {D,C,B,D}: y = 232; + {B,A,C,D}: y = 76; + {B,B,D,D}: y = 96; + {D,D,B,B}: y = 246; + {C,D,A,A}: y = 177; + {D,D,A,B}: y = 242; + {A,A,D,A}: y = 13; + {B,B,A,D}: y = 84; + {B,C,D,C}: y = 111; + {D,A,A,B}: y = 194; + {C,A,B,C}: y = 135; + {D,A,A,C}: y = 195; + {B,B,A,B}: y = 82; + {D,C,D,D}: y = 240; + {B,C,C,D}: y = 108; + {D,B,A,C}: y = 211; + {A,C,D,D}: y = 48; + {D,A,A,A}: y = 193; + {C,A,A,B}: y = 130; + {D,B,A,D}: y = 212; + {D,A,B,B}: y = 198; + {A,C,B,A}: y = 37; + {B,D,B,D}: y = 120; + {C,C,B,C}: y = 167; + {D,B,A,B}: y = 210; + {A,B,A,B}: y = 18; + {B,C,B,B}: y = 102; + {B,B,A,A}: y = 81; + {D,D,A,D}: y = 244; + {A,B,D,B}: y = 30; + {A,C,A,C}: y = 35; + {A,A,C,D}: y = 12; + {B,D,B,C}: y = 119; + {B,C,A,C}: y = 99; + {D,A,C,A}: y = 201; + {B,A,A,D}: y = 68; + {C,A,A,D}: y = 132; + {B,A,C,A}: y = 73; + {C,C,A,D}: y = 164; + {B,D,B,A}: y = 117; + {A,D,D,B}: y = 62; + {B,D,D,C}: y = 127; + {A,B,D,A}: y = 29; + {C,D,B,A}: y = 181; + {B,B,C,B}: y = 90; + {B,D,A,B}: y = 114; + {B,D,D,D}: y = 128; + {C,A,C,A}: y = 137; + {A,A,B,A}: y = 5; + {C,A,D,D}: y = 144; + {D,C,B,C}: y = 231; + {D,A,C,D}: y = 204; + {C,A,A,C}: y = 131; + {C,B,D,B}: y = 158; + {B,A,A,A}: y = 65; + {D,A,D,C}: y = 207; + {D,B,B,A}: y = 213; + {D,B,D,A}: y = 221; + {C,B,C,C}: y = 155; + + default: y = 0; + + endcase +endmodule diff --git a/tests/simple/const_branch_finish.v b/tests/simple/const_branch_finish.v index f585be87a..7e365eeb4 100644 --- a/tests/simple/const_branch_finish.v +++ b/tests/simple/const_branch_finish.v @@ -4,7 +4,7 @@ $finish; \ end -module top; +module case_branch_finish_top; parameter WIDTH = 32; integer j; initial begin diff --git a/tests/simple/const_fold_func.v b/tests/simple/const_fold_func.v index ee2f12e06..b3f476ce3 100644 --- a/tests/simple/const_fold_func.v +++ b/tests/simple/const_fold_func.v @@ -1,4 +1,4 @@ -module top( +module const_fold_func_top( input wire [3:0] inp, output wire [3:0] out1, out2, out3, out4, out5, output reg [3:0] out6 diff --git a/tests/simple/const_func_shadow.v b/tests/simple/const_func_shadow.v index ca63606d9..fb4f148f6 100644 --- a/tests/simple/const_func_shadow.v +++ b/tests/simple/const_func_shadow.v @@ -1,4 +1,4 @@ -module top(w, x, y, z); +module const_func_shadow_top(w, x, y, z); function [11:0] func; input reg [2:0] x; input reg [2:0] y; diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv index b0a087ecb..77d7ba26b 100644 --- a/tests/simple/defvalue.sv +++ b/tests/simple/defvalue.sv @@ -1,4 +1,4 @@ -module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2); +module defvalue_top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2); cnt #(1) foo (.clock, .cnt(cnt1), .delta); cnt #(2) bar (.clock, .cnt(cnt2)); endmodule diff --git a/tests/simple/func_block.v b/tests/simple/func_block.v index be759d1a9..0ac7ca3bf 100644 --- a/tests/simple/func_block.v +++ b/tests/simple/func_block.v @@ -1,6 +1,6 @@ `default_nettype none -module top(inp, out1, out2, out3); +module func_block_top(inp, out1, out2, out3); input wire [31:0] inp; function automatic [31:0] func1; diff --git a/tests/simple/func_recurse.v b/tests/simple/func_recurse.v index d61c8cc06..02cfbcddf 100644 --- a/tests/simple/func_recurse.v +++ b/tests/simple/func_recurse.v @@ -1,4 +1,4 @@ -module top( +module func_recurse_top( input wire [3:0] inp, output wire [3:0] out1, out2 ); diff --git a/tests/simple/func_width_scope.v b/tests/simple/func_width_scope.v index ce81e894e..2f82988ae 100644 --- a/tests/simple/func_width_scope.v +++ b/tests/simple/func_width_scope.v @@ -1,4 +1,4 @@ -module top(inp, out1, out2); +module func_width_scope_top(inp, out1, out2); input wire signed inp; localparam WIDTH_A = 5; diff --git a/tests/simple/genblk_collide.v b/tests/simple/genblk_collide.v index f42dd2cfc..118c0b008 100644 --- a/tests/simple/genblk_collide.v +++ b/tests/simple/genblk_collide.v @@ -1,6 +1,6 @@ `default_nettype none -module top1; +module genblock_collide_top1; generate if (1) begin : foo if (1) begin : bar @@ -12,7 +12,7 @@ module top1; endgenerate endmodule -module top2; +module genblock_collide_top2; genvar i; generate if (1) begin : foo diff --git a/tests/simple/genblk_dive.v b/tests/simple/genblk_dive.v index 98d0e1f4b..ca0c0d4a1 100644 --- a/tests/simple/genblk_dive.v +++ b/tests/simple/genblk_dive.v @@ -1,5 +1,5 @@ `default_nettype none -module top(output wire x); +module genblk_dive_top(output wire x); generate if (1) begin : Z if (1) begin : A diff --git a/tests/simple/genblk_order.v b/tests/simple/genblk_order.v index 7c3a7a756..c80c1ac1a 100644 --- a/tests/simple/genblk_order.v +++ b/tests/simple/genblk_order.v @@ -1,5 +1,5 @@ `default_nettype none -module top( +module genblk_order_top( output wire out1, output wire out2 ); diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v index a04631a20..c1348632c 100644 --- a/tests/simple/genblk_port_shadow.v +++ b/tests/simple/genblk_port_shadow.v @@ -1,4 +1,4 @@ -module top(x); +module genblock_port_shadow_top(x); generate if (1) begin : blk wire x; diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v index 123afaeab..b03044fde 100644 --- a/tests/simple/hierarchy.v +++ b/tests/simple/hierarchy.v @@ -1,6 +1,6 @@ (* top *) -module top(a, b, y1, y2, y3, y4); +module hierarchy_top(a, b, y1, y2, y3, y4); input [3:0] a; input signed [3:0] b; output [7:0] y1, y2, y3, y4; diff --git a/tests/simple/ifdef_1.v b/tests/simple/ifdef_1.v index fa962355c..f1358185c 100644 --- a/tests/simple/ifdef_1.v +++ b/tests/simple/ifdef_1.v @@ -1,4 +1,4 @@ -module top(o1, o2, o3, o4); +module ifdef_1_top(o1, o2, o3, o4); `define FAIL input wire not_a_port; diff --git a/tests/simple/ifdef_2.v b/tests/simple/ifdef_2.v index 6dd89efed..9fae7570d 100644 --- a/tests/simple/ifdef_2.v +++ b/tests/simple/ifdef_2.v @@ -1,4 +1,4 @@ -module top(o1, o2, o3); +module ifdef_2_top(o1, o2, o3); output wire o1; diff --git a/tests/simple/lesser_size_cast.sv b/tests/simple/lesser_size_cast.sv new file mode 100644 index 000000000..8c0bc9814 --- /dev/null +++ b/tests/simple/lesser_size_cast.sv @@ -0,0 +1,7 @@ +module top ( + input signed [1:0] a, + input signed [2:0] b, + output signed [4:0] c +); + assign c = 2'(a) * b; +endmodule diff --git a/tests/simple/local_loop_var.sv b/tests/simple/local_loop_var.sv index 46b4e5c22..42860e218 100644 --- a/tests/simple/local_loop_var.sv +++ b/tests/simple/local_loop_var.sv @@ -1,4 +1,4 @@ -module top(out); +module local_loop_top(out); output integer out; initial begin integer i; diff --git a/tests/simple/loop_prefix_case.v b/tests/simple/loop_prefix_case.v new file mode 100644 index 000000000..0cfa00547 --- /dev/null +++ b/tests/simple/loop_prefix_case.v @@ -0,0 +1,18 @@ +module loop_prefix_case_top( + input wire x, + output reg y +); + localparam I = 1; + genvar i; + generate + for (i = 0; i < 1; i = i + 1) begin : blk + wire [i:i] z = x; + end + endgenerate + always @* begin + case (blk[I - 1].z) + 1: y = 0; + 0: y = 1; + endcase + end +endmodule diff --git a/tests/simple/loop_var_shadow.v b/tests/simple/loop_var_shadow.v index 0222a4493..b75a15ab0 100644 --- a/tests/simple/loop_var_shadow.v +++ b/tests/simple/loop_var_shadow.v @@ -1,4 +1,4 @@ -module top(out); +module loop_var_shadow_top(out); genvar i; generate for (i = 0; i < 2; i = i + 1) begin : loop diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv index 75c4cd136..5fc9e2881 100644 --- a/tests/simple/macro_arg_spaces.sv +++ b/tests/simple/macro_arg_spaces.sv @@ -1,4 +1,4 @@ -module top( +module macro_arg_spaces_top( input wire [31:0] i, output wire [31:0] x, y, z ); diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v index 3dbb5ea01..e0239c08b 100644 --- a/tests/simple/macro_arg_surrounding_spaces.v +++ b/tests/simple/macro_arg_surrounding_spaces.v @@ -1,4 +1,4 @@ -module top( +module macr_arg_surrounding_spaces_top( IDENT_V_, IDENT_W_, IDENT_X_, diff --git a/tests/simple/matching_end_labels.sv b/tests/simple/matching_end_labels.sv new file mode 100644 index 000000000..2d42e7e10 --- /dev/null +++ b/tests/simple/matching_end_labels.sv @@ -0,0 +1,29 @@ +module matching_end_labels_top( + output reg [7:0] + out1, out2, out3, out4 +); + initial begin + begin : blk1 + reg x; + x = 1; + end + out1 = blk1.x; + begin : blk2 + reg x; + x = 2; + end : blk2 + out2 = blk2.x; + end + if (1) begin + if (1) begin : blk3 + reg x; + assign x = 3; + end + assign out3 = blk3.x; + if (1) begin : blk4 + reg x; + assign x = 4; + end : blk4 + assign out4 = blk4.x; + end +endmodule diff --git a/tests/simple/mem2reg_bounds_tern.v b/tests/simple/mem2reg_bounds_tern.v new file mode 100644 index 000000000..0e6852fe7 --- /dev/null +++ b/tests/simple/mem2reg_bounds_tern.v @@ -0,0 +1,19 @@ +module mem2reg_bounds_term_top( + input clk, + input wire [1:0] sel, + input wire [7:0] base, + output reg [7:0] line +); + reg [0:7] mem [0:2]; + + generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin : gen + always @(posedge clk) + mem[i] <= i == 0 ? base : mem[i - 1] + 1; + end + endgenerate + + always @(posedge clk) + line = mem[sel]; +endmodule diff --git a/tests/simple/memwr_port_connection.sv b/tests/simple/memwr_port_connection.sv new file mode 100644 index 000000000..5bf414e08 --- /dev/null +++ b/tests/simple/memwr_port_connection.sv @@ -0,0 +1,13 @@ +module producer( + output logic [3:0] out +); + assign out = 4'hA; +endmodule + +module top( + output logic [3:0] out +); + logic [3:0] v[0:0]; + producer p(v[0]); + assign out = v[0]; +endmodule diff --git a/tests/simple/module_scope.v b/tests/simple/module_scope.v new file mode 100644 index 000000000..d07783912 --- /dev/null +++ b/tests/simple/module_scope.v @@ -0,0 +1,29 @@ +`default_nettype none + +module module_scope_Example(o1, o2); + parameter [31:0] v1 = 10; + parameter [31:0] v2 = 20; + output [31:0] o1, o2; + assign module_scope_Example.o1 = module_scope_Example.v1; + assign module_scope_Example.o2 = module_scope_Example.v2; +endmodule + +module module_scope_ExampleLong(o1, o2); + parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10; + parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20; + output [31:0] o1, o2; + assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1; + assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2; +endmodule + +module module_scope_top( + output [31:0] a1, a2, b1, b2, c1, c2, + output [31:0] d1, d2, e1, e2, f1, f2 +); + module_scope_Example a(a1, a2); + module_scope_Example #(1) b(b1, b2); + module_scope_Example #(1, 2) c(c1, c2); + module_scope_ExampleLong d(d1, d2); + module_scope_ExampleLong #(1) e(e1, e2); + module_scope_ExampleLong #(1, 2) f(f1, f2); +endmodule diff --git a/tests/simple/module_scope_case.v b/tests/simple/module_scope_case.v new file mode 100644 index 000000000..bceba4424 --- /dev/null +++ b/tests/simple/module_scope_case.v @@ -0,0 +1,11 @@ +module module_scope_case_top( + input wire x, + output reg y +); + always @* begin + case (module_scope_case_top.x) + 1: module_scope_case_top.y = 0; + 0: module_scope_case_top.y = 1; + endcase + end +endmodule diff --git a/tests/simple/named_genblk.v b/tests/simple/named_genblk.v index b8300fc4d..b98b7c8ce 100644 --- a/tests/simple/named_genblk.v +++ b/tests/simple/named_genblk.v @@ -1,5 +1,5 @@ `default_nettype none -module top; +module named_genblk_top; generate if (1) begin wire t; diff --git a/tests/simple/nested_genblk_resolve.v b/tests/simple/nested_genblk_resolve.v index da5593f8a..70bbc611b 100644 --- a/tests/simple/nested_genblk_resolve.v +++ b/tests/simple/nested_genblk_resolve.v @@ -1,5 +1,5 @@ `default_nettype none -module top; +module nested_genblk_resolve_top; generate if (1) begin wire x; diff --git a/tests/simple/signed_full_slice.v b/tests/simple/signed_full_slice.v new file mode 100644 index 000000000..f8a331578 --- /dev/null +++ b/tests/simple/signed_full_slice.v @@ -0,0 +1,29 @@ +module pass_through_a( + input wire [31:0] inp, + output wire [31:0] out +); + assign out[31:0] = inp[31:0]; +endmodule + +module top_a( + input wire signed [31:0] inp, + output wire signed [31:0] out +); + pass_through_a pt(inp[31:0], out[31:0]); +endmodule + +// tests both module declaration orderings + +module top_b( + input wire signed [31:0] inp, + output wire signed [31:0] out +); + pass_through_b pt(inp[31:0], out[31:0]); +endmodule + +module pass_through_b( + input wire [31:0] inp, + output wire [31:0] out +); + assign out[31:0] = inp[31:0]; +endmodule diff --git a/tests/simple/string_format.v b/tests/simple/string_format.v index ce45ca1e9..cb7b419ac 100644 --- a/tests/simple/string_format.v +++ b/tests/simple/string_format.v @@ -1,4 +1,4 @@ -module top; +module string_format_top; parameter STR = "something interesting"; initial begin $display("A: %s", STR); diff --git a/tests/simple/unnamed_block_decl.sv b/tests/simple/unnamed_block_decl.sv index e81b457a8..e78c577da 100644 --- a/tests/simple/unnamed_block_decl.sv +++ b/tests/simple/unnamed_block_decl.sv @@ -1,4 +1,4 @@ -module top(z); +module unnamed_block_decl(z); output integer z; initial begin integer x; diff --git a/tests/simple/verilog_primitives.v b/tests/simple/verilog_primitives.v new file mode 100644 index 000000000..0ee07393b --- /dev/null +++ b/tests/simple/verilog_primitives.v @@ -0,0 +1,15 @@ +module verilog_primitives ( + input wire in1, in2, in3, + output wire out_buf0, out_buf1, out_buf2, out_buf3, out_buf4, + output wire out_not0, out_not1, out_not2, + output wire out_xnor +); + +buf u_buf0 (out_buf0, in1); +buf u_buf1 (out_buf1, out_buf2, out_buf3, out_buf4, in2); + +not u_not0 (out_not0, out_not1, out_not2, in1); + +xnor u_xnor0 (out_xnor, in1, in2, in3); + +endmodule diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index 3bb3cf992..5fcedbff1 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -1,6 +1,6 @@ // test cases found using vloghammer -// https://github.com/cliffordwolf/VlogHammer +// https://github.com/YosysHQ/VlogHammer module test01(a, y); input [7:0] a; diff --git a/tests/simple/wandwor.v b/tests/simple/wandwor.v index 34404aa26..40502acfc 100644 --- a/tests/simple/wandwor.v +++ b/tests/simple/wandwor.v @@ -5,9 +5,9 @@ module wandwor_test0 (A, B, C, D, X, Y, Z); output Z; assign X = A, X = B, Y = C, Y = D; - foo foo_0 (C, D, X); - foo foo_1 (A, B, Y); - foo foo_2 (X, Y, Z); + wandwor_foo foo_0 (C, D, X); + wandwor_foo foo_1 (A, B, Y); + wandwor_foo foo_2 (X, Y, Z); endmodule module wandwor_test1 (A, B, C, D, X, Y, Z); @@ -16,7 +16,7 @@ module wandwor_test1 (A, B, C, D, X, Y, Z); output wand [3:0] Y; output Z; - bar bar_inst ( + wandwor_bar bar_inst ( .I0({A, B}), .I1({B, A}), .O({X, Y}) @@ -27,10 +27,10 @@ module wandwor_test1 (A, B, C, D, X, Y, Z); assign Z = ^{X,Y}; endmodule -module foo(input I0, I1, output O); +module wandwor_foo(input I0, I1, output O); assign O = I0 ^ I1; endmodule -module bar(input [7:0] I0, I1, output [7:0] O); +module wandwor_bar(input [7:0] I0, I1, output [7:0] O); assign O = I0 + I1; endmodule diff --git a/tests/simple_abc9/abc9.box b/tests/simple_abc9/abc9.box deleted file mode 100644 index b3c88437c..000000000 --- a/tests/simple_abc9/abc9.box +++ /dev/null @@ -1,3 +0,0 @@ -MUXF8 1 0 3 1 -#I0 I1 S -0 0 0 # O diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 5e969c614..fba089b1f 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box_id=1, blackbox *) +(* abc9_box, blackbox *) module MUXF8(input I0, I1, S, output O); specify (I0 => O) = 0; @@ -300,15 +300,29 @@ endmodule module abc9_test036(input A, B, S, output [1:0] O); (* keep *) MUXF8 m ( - .I0(I0), - .I1(I1), + .I0(A), + .I1(B), .O(O[0]), .S(S) ); MUXF8 m2 ( - .I0(I0), - .I1(I1), + .I0(A), + .I1(B), .O(O[1]), .S(S) ); endmodule + +(* abc9_box, whitebox *) +module MUXF7(input I0, I1, S, output O); +assign O = S ? I1 : I0; +specify + (I0 => O) = 0; + (I1 => O) = 0; + (S => O) = 0; +endspecify +endmodule + +module abc9_test037(output o); +MUXF7 m(.I0(1'b1), .I1(1'b0), .S(o), .O(o)); +endmodule diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index b48505e29..4a5bf01a3 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -37,14 +37,18 @@ done cp ../simple/*.v . cp ../simple/*.sv . +rm specify.v # bug 2675 DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p '\ +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-f \"verilog -noblackbox -specify\" -n 300 -p '\ + read_verilog -icells -lib +/abc9_model.v; \ hierarchy; \ synth -run coarse; \ opt -full; \ techmap; \ - abc9 -lut 4 -box ../abc9.box; \ + abc9 -lut 4; \ clean; \ - check -assert; \ + check -assert * abc9_test037 %d; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ - setattr -mod -unset blackbox'" + setattr -mod -unset blackbox -unset whitebox'" + +# NOTE: Skip 'check -assert' on abc9_test037 because it intentionally has a combinatorial loop diff --git a/tests/svinterfaces/load_and_derive.sv b/tests/svinterfaces/load_and_derive.sv new file mode 100644 index 000000000..0de0de3b3 --- /dev/null +++ b/tests/svinterfaces/load_and_derive.sv @@ -0,0 +1,20 @@ +// This test checks that we correctly elaborate interfaces in modules, even if they are loaded on +// demand. The "ondemand" module is defined in ondemand.sv in this directory and will be read as +// part of the hierarchy pass. + +interface iface; + logic [7:0] x; + logic [7:0] y; +endinterface + +module dut (input logic [7:0] x, output logic [7:0] y); + iface intf(); + assign intf.x = x; + assign y = intf.y; + + ondemand u(.intf); +endmodule + +module ref (input logic [7:0] x, output logic [7:0] y); + assign y = ~x; +endmodule diff --git a/tests/svinterfaces/load_and_derive.ys b/tests/svinterfaces/load_and_derive.ys new file mode 100644 index 000000000..067235ec2 --- /dev/null +++ b/tests/svinterfaces/load_and_derive.ys @@ -0,0 +1,6 @@ +read_verilog -sv load_and_derive.sv +hierarchy -libdir . -check +flatten +equiv_make ref dut equiv +equiv_simple +equiv_status -assert diff --git a/tests/svinterfaces/ondemand.sv b/tests/svinterfaces/ondemand.sv new file mode 100644 index 000000000..70d6048f8 --- /dev/null +++ b/tests/svinterfaces/ondemand.sv @@ -0,0 +1,5 @@ +// This is used by the load_and_derive test. + +module ondemand (iface intf); + assign intf.y = ~intf.x; +endmodule diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh index 86567d1c1..9ef53926c 100755 --- a/tests/svinterfaces/run-test.sh +++ b/tests/svinterfaces/run-test.sh @@ -1,6 +1,6 @@ #/bin/bash -e - - ./runone.sh svinterface1 ./runone.sh svinterface_at_top + +./run_simple.sh load_and_derive diff --git a/tests/svinterfaces/run_simple.sh b/tests/svinterfaces/run_simple.sh new file mode 100755 index 000000000..bce994443 --- /dev/null +++ b/tests/svinterfaces/run_simple.sh @@ -0,0 +1,15 @@ +#!/bin/bash + +# Run a simple test with a .ys file + +if [ $# != 1 ]; then + echo >&2 "Expected 1 argument" + exit 1 +fi + +echo -n "Test: $1 ->" +../../yosys $1.ys >$1.log_stdout 2>$1.log_stderr || { + echo "ERROR!" + exit 1 +} +echo "ok" diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys index 7b079c136..776d2e985 100644 --- a/tests/svtypes/logic_rom.ys +++ b/tests/svtypes/logic_rom.ys @@ -1,3 +1,3 @@ read_verilog -sv logic_rom.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=8 %i diff --git a/tests/svtypes/typedef_initial_and_assign.sv b/tests/svtypes/typedef_initial_and_assign.sv new file mode 100644 index 000000000..05579947d --- /dev/null +++ b/tests/svtypes/typedef_initial_and_assign.sv @@ -0,0 +1,94 @@ +package pkg; + typedef logic pkg_user_t; +endpackage + +module top; + typedef logic user_t; + + // Continuous assignment to a variable is legal + user_t var_1; + assign var_1 = 0; + assert property (var_1 == 0); + + var user_t var_2; + assign var_2 = 0; + assert property (var_2 == 0); + + var pkg::pkg_user_t var_3; + assign var_3 = 0; + assert property (var_3 == 0); + + // Procedural assignment to a variable is legal + user_t var_4 = 0; + assert property (var_4 == 0); + + user_t var_5; + initial var_5 = 0; + assert property (var_5 == 0); + + var user_t var_6 = 0; + assert property (var_6 == 0); + + var user_t var_7; + initial var_7 = 0; + assert property (var_7 == 0); + + pkg::pkg_user_t var_8 = 0; + assert property (var_8 == 0); + + pkg::pkg_user_t var_9; + initial var_9 = 0; + assert property (var_9 == 0); + + var pkg::pkg_user_t var_10 = 0; + assert property (var_10 == 0); + + var pkg::pkg_user_t var_11; + initial var_11 = 0; + assert property (var_11 == 0); + + // Continuous assignment to a net is legal + wire user_t wire_1 = 0; + assert property (wire_3 == 0); + + wire user_t wire_2; + assign wire_2 = 0; + assert property (wire_2 == 0); + + wire pkg::pkg_user_t wire_3 = 0; + assert property (wire_3 == 0); + + wire pkg::pkg_user_t wire_4; + assign wire_4 = 0; + assert property (wire_4 == 0); + + // Mixing continuous and procedural assignments is illegal + user_t var_12 = 0; + assign var_12 = 1; // warning: reg assigned in a continuous assignment + + user_t var_13; + initial var_13 = 0; + assign var_13 = 1; // warning: reg assigned in a continuous assignment + + var user_t var_14 = 0; + assign var_14 = 1; // warning: reg assigned in a continuous assignment + + var user_t var_15; + initial var_15 = 0; + assign var_15 = 1; // warning: reg assigned in a continuous assignment + + pkg::pkg_user_t var_16 = 0; + assign var_16 = 1; // warning: reg assigned in a continuous assignment + + pkg::pkg_user_t var_17; + initial var_17 = 0; + assign var_17 = 1; // warning: reg assigned in a continuous assignment + + var pkg::pkg_user_t var_18 = 0; + assign var_18 = 1; // warning: reg assigned in a continuous assignment + + var pkg::pkg_user_t var_19; + initial var_19 = 0; + assign var_19 = 1; // warning: reg assigned in a continuous assignment + +endmodule diff --git a/tests/svtypes/typedef_initial_and_assign.ys b/tests/svtypes/typedef_initial_and_assign.ys new file mode 100644 index 000000000..de456bb82 --- /dev/null +++ b/tests/svtypes/typedef_initial_and_assign.ys @@ -0,0 +1,14 @@ +logger -expect-no-warnings +logger -expect warning "reg '\\var_12' is assigned in a continuous assignment" 1 +logger -expect warning "reg '\\var_13' is assigned in a continuous assignment" 1 +logger -expect warning "reg '\\var_14' is assigned in a continuous assignment" 1 +logger -expect warning "reg '\\var_15' is assigned in a continuous assignment" 1 +logger -expect warning "reg '\\var_16' is assigned in a continuous assignment" 1 +logger -expect warning "reg '\\var_17' is assigned in a continuous assignment" 1 +logger -expect warning "reg '\\var_18' is assigned in a continuous assignment" 1 +logger -expect warning "reg '\\var_19' is assigned in a continuous assignment" 1 + +read_verilog -sv typedef_initial_and_assign.sv +hierarchy; proc; opt +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all
\ No newline at end of file diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys index 93cf47bbe..d47ee9929 100644 --- a/tests/svtypes/typedef_memory.ys +++ b/tests/svtypes/typedef_memory.ys @@ -1,3 +1,3 @@ read_verilog -sv typedef_memory.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys index 854e554f3..bfebd05fc 100644 --- a/tests/svtypes/typedef_memory_2.ys +++ b/tests/svtypes/typedef_memory_2.ys @@ -1,4 +1,4 @@ read_verilog -sv typedef_memory_2.sv prep -top top dump -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv index 5507d84f2..9a898fac8 100644 --- a/tests/svtypes/typedef_scopes.sv +++ b/tests/svtypes/typedef_scopes.sv @@ -4,6 +4,7 @@ typedef enum logic {s0, s1} outer_enum_t; module top; + // globals are inherited outer_uint4_t u4_i = 8'hA5; outer_enum_t enum4_i = s0; always @(*) assert(u4_i == 4'h5); @@ -17,13 +18,22 @@ module top; always @(*) assert(inner_enum1 == 3'h3); if (1) begin: genblock + // type declarations in child scopes shadow their parents typedef logic [7:0] inner_type; parameter inner_type inner_const = 8'hA5; typedef enum logic [2:0] {s5=5, s6, s7} inner_enum_t; + inner_type inner_gb_i = inner_const; //8'hA5; inner_enum_t inner_gb_enum1 = s7; always @(*) assert(inner_gb_i == 8'hA5); always @(*) assert(inner_gb_enum1 == 3'h7); + + // check that copying of struct member types works over multiple type scopes + typedef struct packed { + outer_uint4_t x; + } mystruct_t; + mystruct_t mystruct; + always @(*) assert($bits(mystruct) == 4); end inner_type inner_i2 = 8'h42; diff --git a/tests/techmap/bug2759.ys b/tests/techmap/bug2759.ys new file mode 100644 index 000000000..05699bef8 --- /dev/null +++ b/tests/techmap/bug2759.ys @@ -0,0 +1,14 @@ +read_verilog -specify <<EOT +(* abc9_box, whitebox *) +module box(input [1:0] i, output o); +specify +(i *> o) = 1; +endspecify +assign o = ^i; +endmodule + +module top(input [1:0] i, output o); +box i1(i, o); +endmodule +EOT +abc9 -lut 4 diff --git a/tests/techmap/bug2972.ys b/tests/techmap/bug2972.ys new file mode 100644 index 000000000..8ae895f56 --- /dev/null +++ b/tests/techmap/bug2972.ys @@ -0,0 +1,20 @@ +read_verilog -specify <<EOT +(* abc9_box, blackbox*) +module box(input clk, d, output reg q, output do); +parameter P = 0; +always @(posedge clk) + q <= d; +assign do = d; +specify + (posedge clk => (q : d)) = 1; + (d => do) = 1; +endspecify +endmodule + +module top(input clk, d, output q); +box i1(clk, d, q); +endmodule +EOT +hierarchy +abc9 -lut 4 +abc9 -lut 4 diff --git a/tests/techmap/dfflegalize_adff.ys b/tests/techmap/dfflegalize_adff.ys index 135ae0ab7..fc579e7d6 100644 --- a/tests/techmap/dfflegalize_adff.ys +++ b/tests/techmap/dfflegalize_adff.ys @@ -39,6 +39,8 @@ design -save orig flatten equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x @@ -73,6 +75,36 @@ select -assert-count 14 t:$_DFFE_PP0P_ select -assert-none t:$_DFFE_PP0P_ t:$_NOT_ top/* %% %n t:* %i +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ x + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 2 adffe0/t:$_NOT_ +select -assert-count 2 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ x + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 3 adffe0/t:$_NOT_ +select -assert-count 3 adffe1/t:$_NOT_ +select -assert-count 14 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + + # Convert everything to DFFSRs. design -load orig diff --git a/tests/techmap/dfflegalize_adff_init.ys b/tests/techmap/dfflegalize_adff_init.ys index 7764e15a5..25ed59307 100644 --- a/tests/techmap/dfflegalize_adff_init.ys +++ b/tests/techmap/dfflegalize_adff_init.ys @@ -45,6 +45,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 @@ -144,9 +148,9 @@ design -load orig dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1 select -assert-count 2 adff0/t:$_NOT_ -select -assert-count 16 adff1/t:$_NOT_ +select -assert-count 13 adff1/t:$_NOT_ select -assert-count 3 adffe0/t:$_NOT_ -select -assert-count 22 adffe1/t:$_NOT_ +select -assert-count 18 adffe1/t:$_NOT_ select -assert-count 0 adff0/t:$_MUX_ select -assert-count 3 adff1/t:$_MUX_ select -assert-count 0 adffe0/t:$_MUX_ @@ -164,9 +168,9 @@ select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t design -load orig dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 -select -assert-count 16 adff0/t:$_NOT_ +select -assert-count 13 adff0/t:$_NOT_ select -assert-count 8 adff1/t:$_NOT_ -select -assert-count 22 adffe0/t:$_NOT_ +select -assert-count 18 adffe0/t:$_NOT_ select -assert-count 11 adffe1/t:$_NOT_ select -assert-count 3 adff0/t:$_MUX_ select -assert-count 0 adff1/t:$_MUX_ @@ -185,31 +189,27 @@ select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t design -load orig dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 -select -assert-count 16 adff0/t:$_NOT_ +select -assert-count 10 adff0/t:$_NOT_ select -assert-count 2 adff1/t:$_NOT_ -select -assert-count 22 adffe0/t:$_NOT_ +select -assert-count 14 adffe0/t:$_NOT_ select -assert-count 3 adffe1/t:$_NOT_ select -assert-count 3 adff0/t:$_MUX_ select -assert-count 0 adff1/t:$_MUX_ select -assert-count 4 adffe0/t:$_MUX_ select -assert-count 0 adffe1/t:$_MUX_ -select -assert-count 6 adff0/t:$_DFFE_PP1P_ +select -assert-count 9 adff0/t:$_DFFE_PP1P_ select -assert-count 3 adff1/t:$_DFFE_PP1P_ -select -assert-count 8 adffe0/t:$_DFFE_PP1P_ +select -assert-count 12 adffe0/t:$_DFFE_PP1P_ select -assert-count 4 adffe1/t:$_DFFE_PP1P_ -select -assert-count 3 adff0/t:$_DLATCH_P_ -select -assert-count 0 adff1/t:$_DLATCH_P_ -select -assert-count 4 adffe0/t:$_DLATCH_P_ -select -assert-count 0 adffe1/t:$_DLATCH_P_ -select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i +select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i design -load orig dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 select -assert-count 8 adff0/t:$_NOT_ -select -assert-count 16 adff1/t:$_NOT_ +select -assert-count 13 adff1/t:$_NOT_ select -assert-count 11 adffe0/t:$_NOT_ -select -assert-count 22 adffe1/t:$_NOT_ +select -assert-count 18 adffe1/t:$_NOT_ select -assert-count 0 adff0/t:$_MUX_ select -assert-count 3 adff1/t:$_MUX_ select -assert-count 0 adffe0/t:$_MUX_ @@ -225,6 +225,60 @@ select -assert-count 4 adffe1/t:$_DLATCH_P_ select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 0 + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 2 adffe0/t:$_NOT_ +select -assert-count 2 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 1 + +select -assert-count 8 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 10 adffe0/t:$_NOT_ +select -assert-count 10 adffe1/t:$_NOT_ +select -assert-count 0 adff0/t:$_MUX_ +select -assert-count 0 adff1/t:$_MUX_ +select -assert-count 4 adffe0/t:$_MUX_ +select -assert-count 4 adffe1/t:$_MUX_ +select -assert-count 14 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 0 + +select -assert-count 2 adff0/t:$_NOT_ +select -assert-count 2 adff1/t:$_NOT_ +select -assert-count 3 adffe0/t:$_NOT_ +select -assert-count 3 adffe1/t:$_NOT_ +select -assert-count 14 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 1 + +select -assert-count 8 adff0/t:$_NOT_ +select -assert-count 8 adff1/t:$_NOT_ +select -assert-count 11 adffe0/t:$_NOT_ +select -assert-count 11 adffe1/t:$_NOT_ +select -assert-count 14 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + + # Convert everything to DFFSRs. design -load orig diff --git a/tests/techmap/dfflegalize_adlatch_init.ys b/tests/techmap/dfflegalize_adlatch_init.ys index 7b22ea0c0..a55082d1d 100644 --- a/tests/techmap/dfflegalize_adlatch_init.ys +++ b/tests/techmap/dfflegalize_adlatch_init.ys @@ -45,7 +45,7 @@ select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i design -load orig dfflegalize -cell $_DLATCH_PP0_ 1 -select -assert-count 16 adlatch0/t:$_NOT_ +select -assert-count 13 adlatch0/t:$_NOT_ select -assert-count 8 adlatch1/t:$_NOT_ select -assert-count 3 adlatch0/t:$_MUX_ select -assert-count 0 adlatch1/t:$_MUX_ @@ -68,7 +68,7 @@ design -load orig dfflegalize -cell $_DLATCH_PP1_ 1 select -assert-count 8 adlatch0/t:$_NOT_ -select -assert-count 16 adlatch1/t:$_NOT_ +select -assert-count 13 adlatch1/t:$_NOT_ select -assert-count 0 adlatch0/t:$_MUX_ select -assert-count 3 adlatch1/t:$_MUX_ select -assert-count 3 adlatch0/t:$_DLATCH_PP1_ diff --git a/tests/techmap/dfflegalize_aldff.ys b/tests/techmap/dfflegalize_aldff.ys new file mode 100644 index 000000000..1ee9e3af6 --- /dev/null +++ b/tests/techmap/dfflegalize_aldff.ys @@ -0,0 +1,92 @@ +read_verilog -icells <<EOT + +module aldff(input C, L, AD, D, output [2:0] Q); +$_ALDFF_PP_ ff0 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[0])); +$_ALDFF_PN_ ff1 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[1])); +$_ALDFF_NP_ ff2 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2])); +endmodule + +module aldffe(input C, E, L, AD, D, output [3:0] Q); +$_ALDFFE_PPP_ ff0 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[0])); +$_ALDFFE_PPN_ ff1 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[1])); +$_ALDFFE_PNP_ ff2 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[2])); +$_ALDFFE_NPP_ ff3 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, L, AD, D, output [6:0] Q); +aldff aldff_(.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2:0])); +aldffe aldffe_(.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[6:3])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ x + +select -assert-count 2 aldff/t:$_NOT_ +select -assert-count 2 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ x + +select -assert-count 2 aldff/t:$_NOT_ +select -assert-count 3 aldffe/t:$_NOT_ +select -assert-count 7 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ x + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 3 aldff/t:$_NOT_ +select -assert-count 3 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ x + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 3 aldff/t:$_NOT_ +select -assert-count 4 aldffe/t:$_NOT_ +select -assert-count 7 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_aldff_init.ys b/tests/techmap/dfflegalize_aldff_init.ys new file mode 100644 index 000000000..f4db8dd32 --- /dev/null +++ b/tests/techmap/dfflegalize_aldff_init.ys @@ -0,0 +1,148 @@ +read_verilog -icells <<EOT + +module aldff(input C, L, AD, D, (* init = 3'b000 *) output [2:0] Q); +$_ALDFF_PP_ ff0 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[0])); +$_ALDFF_PN_ ff1 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[1])); +$_ALDFF_NP_ ff2 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2])); +endmodule + +module aldffe(input C, E, L, AD, D, (* init = 4'b0000 *) output [3:0] Q); +$_ALDFFE_PPP_ ff0 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[0])); +$_ALDFFE_PPN_ ff1 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[1])); +$_ALDFFE_PNP_ ff2 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[2])); +$_ALDFFE_NPP_ ff3 (.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[3])); +endmodule + +module top(input C, E, L, AD, D, output [6:0] Q); +aldff aldff_(.C(C), .L(L), .AD(AD), .D(D), .Q(Q[2:0])); +aldffe aldffe_(.C(C), .L(L), .AD(AD), .E(E), .D(D), .Q(Q[6:3])); +endmodule + +EOT + +design -save orig +flatten +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 +#equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 0 + +select -assert-count 2 aldff/t:$_NOT_ +select -assert-count 2 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 1 + +select -assert-count 11 aldff/t:$_NOT_ +select -assert-count 14 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 0 + +select -assert-count 2 aldff/t:$_NOT_ +select -assert-count 3 aldffe/t:$_NOT_ +select -assert-count 7 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 1 + +select -assert-count 11 aldff/t:$_NOT_ +select -assert-count 15 aldffe/t:$_NOT_ +select -assert-count 7 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 0 + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 3 aldff/t:$_NOT_ +select -assert-count 3 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ 1 + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 12 aldff/t:$_NOT_ +select -assert-count 15 aldffe/t:$_NOT_ +select -assert-count 0 aldff/t:$_MUX_ +select -assert-count 4 aldffe/t:$_MUX_ +select -assert-count 7 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 0 + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 3 aldff/t:$_NOT_ +select -assert-count 4 aldffe/t:$_NOT_ +select -assert-count 7 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ 1 + +select -assert-count 2 aldff/t:$_AND_ +select -assert-count 3 aldffe/t:$_AND_ +select -assert-count 2 aldff/t:$_ANDNOT_ +select -assert-count 3 aldffe/t:$_ANDNOT_ +select -assert-count 1 aldff/t:$_OR_ +select -assert-count 1 aldffe/t:$_OR_ +select -assert-count 1 aldff/t:$_ORNOT_ +select -assert-count 1 aldffe/t:$_ORNOT_ +select -assert-count 12 aldff/t:$_NOT_ +select -assert-count 16 aldffe/t:$_NOT_ +select -assert-count 7 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ t:$_ORNOT_ top/* %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dff.ys b/tests/techmap/dfflegalize_dff.ys index 63ab47865..374289678 100644 --- a/tests/techmap/dfflegalize_dff.ys +++ b/tests/techmap/dfflegalize_dff.ys @@ -70,6 +70,8 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFF_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ x equiv_opt -assert -multiclock dfflegalize -cell $_SDFF_PP0_ x @@ -176,6 +178,56 @@ select -assert-count 27 t:$_DFFE_PP0P_ select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ x + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + # Convert everything to DFFSRs. design -load orig @@ -237,25 +289,18 @@ select -assert-count 2 sdff0/t:$_NOT_ select -assert-count 8 sdff1/t:$_NOT_ select -assert-count 2 sdffe0/t:$_NOT_ select -assert-count 10 sdffe1/t:$_NOT_ -select -assert-count 2 sdffce0/t:$_NOT_ -select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ select -assert-count 0 dff/t:$_MUX_ select -assert-count 3 dffe/t:$_MUX_ select -assert-count 0 sdff0/t:$_MUX_ select -assert-count 0 sdff1/t:$_MUX_ select -assert-count 4 sdffe0/t:$_MUX_ select -assert-count 4 sdffe1/t:$_MUX_ -select -assert-count 4 sdffce0/t:$_MUX_ -select -assert-count 4 sdffce1/t:$_MUX_ -select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* sdffce1/* %u %n %i -select -assert-count 2 sdffce0/t:$_AND_ -select -assert-count 2 sdffce1/t:$_AND_ -select -assert-count 1 sdffce0/t:$_ORNOT_ -select -assert-count 1 sdffce1/t:$_ORNOT_ -select -assert-count 1 sdffce0/t:$_ANDNOT_ -select -assert-count 1 sdffce1/t:$_ANDNOT_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ select -assert-count 27 t:$_SDFF_PP0_ -select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i +select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i # Convert everything to SDFFEs. diff --git a/tests/techmap/dfflegalize_dff_init.ys b/tests/techmap/dfflegalize_dff_init.ys index 741ac39d0..a170249c7 100644 --- a/tests/techmap/dfflegalize_dff_init.ys +++ b/tests/techmap/dfflegalize_dff_init.ys @@ -78,6 +78,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP0P_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFE_PP1P_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSR_PPP_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 0 @@ -371,6 +375,100 @@ select -assert-count 27 t:$_DFFE_PP1P_ select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 1 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 7 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 3 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 0 + +select -assert-count 1 dff/t:$_NOT_ +select -assert-count 2 dffe/t:$_NOT_ +select -assert-count 1 sdff0/t:$_NOT_ +select -assert-count 1 sdff1/t:$_NOT_ +select -assert-count 1 sdffe0/t:$_NOT_ +select -assert-count 1 sdffe1/t:$_NOT_ +select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 1 + +select -assert-count 5 dff/t:$_NOT_ +select -assert-count 8 dffe/t:$_NOT_ +select -assert-count 7 sdff0/t:$_NOT_ +select -assert-count 7 sdff1/t:$_NOT_ +select -assert-count 9 sdffe0/t:$_NOT_ +select -assert-count 9 sdffe1/t:$_NOT_ +select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 0 dff/t:$_MUX_ +select -assert-count 0 dffe/t:$_MUX_ +select -assert-count 3 sdff0/t:$_MUX_ +select -assert-count 3 sdff1/t:$_MUX_ +select -assert-count 8 sdffe0/t:$_MUX_ +select -assert-count 8 sdffe1/t:$_MUX_ +select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 4 sdffce1/t:$_MUX_ +select -assert-count 27 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i + + # Convert everything to DFFSRs. design -load orig @@ -476,7 +574,7 @@ select -assert-count 2 sdff0/t:$_NOT_ select -assert-count 1 sdff1/t:$_NOT_ select -assert-count 2 sdffe0/t:$_NOT_ select -assert-count 1 sdffe1/t:$_NOT_ -select -assert-count 2 sdffce0/t:$_NOT_ +select -assert-count 1 sdffce0/t:$_NOT_ select -assert-count 1 sdffce1/t:$_NOT_ select -assert-count 0 dff/t:$_MUX_ select -assert-count 3 dffe/t:$_MUX_ @@ -484,14 +582,10 @@ select -assert-count 0 sdff0/t:$_MUX_ select -assert-count 3 sdff1/t:$_MUX_ select -assert-count 4 sdffe0/t:$_MUX_ select -assert-count 8 sdffe1/t:$_MUX_ -select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ select -assert-count 8 sdffce1/t:$_MUX_ -select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i -select -assert-count 2 sdffce0/t:$_AND_ -select -assert-count 1 sdffce0/t:$_ORNOT_ -select -assert-count 1 sdffce0/t:$_ANDNOT_ select -assert-count 27 t:$_SDFF_PP0_ -select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i +select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i design -load orig dfflegalize -cell $_SDFF_PP0_ 1 @@ -503,7 +597,7 @@ select -assert-count 8 sdff1/t:$_NOT_ select -assert-count 9 sdffe0/t:$_NOT_ select -assert-count 10 sdffe1/t:$_NOT_ select -assert-count 9 sdffce0/t:$_NOT_ -select -assert-count 10 sdffce1/t:$_NOT_ +select -assert-count 9 sdffce1/t:$_NOT_ select -assert-count 0 dff/t:$_MUX_ select -assert-count 3 dffe/t:$_MUX_ select -assert-count 3 sdff0/t:$_MUX_ @@ -511,13 +605,9 @@ select -assert-count 0 sdff1/t:$_MUX_ select -assert-count 8 sdffe0/t:$_MUX_ select -assert-count 4 sdffe1/t:$_MUX_ select -assert-count 8 sdffce0/t:$_MUX_ -select -assert-count 4 sdffce1/t:$_MUX_ -select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i -select -assert-count 2 sdffce1/t:$_AND_ -select -assert-count 1 sdffce1/t:$_ORNOT_ -select -assert-count 1 sdffce1/t:$_ANDNOT_ +select -assert-count 8 sdffce1/t:$_MUX_ select -assert-count 27 t:$_SDFF_PP0_ -select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i +select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i design -load orig dfflegalize -cell $_SDFF_PP1_ 0 @@ -529,7 +619,7 @@ select -assert-count 2 sdff1/t:$_NOT_ select -assert-count 1 sdffe0/t:$_NOT_ select -assert-count 2 sdffe1/t:$_NOT_ select -assert-count 1 sdffce0/t:$_NOT_ -select -assert-count 2 sdffce1/t:$_NOT_ +select -assert-count 1 sdffce1/t:$_NOT_ select -assert-count 0 dff/t:$_MUX_ select -assert-count 3 dffe/t:$_MUX_ select -assert-count 3 sdff0/t:$_MUX_ @@ -537,13 +627,9 @@ select -assert-count 0 sdff1/t:$_MUX_ select -assert-count 8 sdffe0/t:$_MUX_ select -assert-count 4 sdffe1/t:$_MUX_ select -assert-count 8 sdffce0/t:$_MUX_ -select -assert-count 4 sdffce1/t:$_MUX_ -select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i -select -assert-count 2 sdffce1/t:$_AND_ -select -assert-count 1 sdffce1/t:$_ORNOT_ -select -assert-count 1 sdffce1/t:$_ANDNOT_ +select -assert-count 8 sdffce1/t:$_MUX_ select -assert-count 27 t:$_SDFF_PP1_ -select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i +select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i design -load orig dfflegalize -cell $_SDFF_PP1_ 1 @@ -554,7 +640,7 @@ select -assert-count 8 sdff0/t:$_NOT_ select -assert-count 7 sdff1/t:$_NOT_ select -assert-count 10 sdffe0/t:$_NOT_ select -assert-count 9 sdffe1/t:$_NOT_ -select -assert-count 10 sdffce0/t:$_NOT_ +select -assert-count 9 sdffce0/t:$_NOT_ select -assert-count 9 sdffce1/t:$_NOT_ select -assert-count 0 dff/t:$_MUX_ select -assert-count 3 dffe/t:$_MUX_ @@ -562,14 +648,10 @@ select -assert-count 0 sdff0/t:$_MUX_ select -assert-count 3 sdff1/t:$_MUX_ select -assert-count 4 sdffe0/t:$_MUX_ select -assert-count 8 sdffe1/t:$_MUX_ -select -assert-count 4 sdffce0/t:$_MUX_ +select -assert-count 8 sdffce0/t:$_MUX_ select -assert-count 8 sdffce1/t:$_MUX_ -select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i -select -assert-count 2 sdffce0/t:$_AND_ -select -assert-count 1 sdffce0/t:$_ORNOT_ -select -assert-count 1 sdffce0/t:$_ANDNOT_ select -assert-count 27 t:$_SDFF_PP1_ -select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i +select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i # Convert everything to SDFFEs. diff --git a/tests/techmap/dfflegalize_dlatch.ys b/tests/techmap/dfflegalize_dlatch.ys index b68ea741e..11683bc1a 100644 --- a/tests/techmap/dfflegalize_dlatch.ys +++ b/tests/techmap/dfflegalize_dlatch.ys @@ -11,6 +11,8 @@ design -save orig equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP0_ x equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ x # Convert everything to DFFs. @@ -40,3 +42,23 @@ dfflegalize -cell $_DLATCHSR_PPP_ x select -assert-count 1 t:$_NOT_ select -assert-count 2 t:$_DLATCHSR_PPP_ select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ x + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ x + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dlatch_const.ys b/tests/techmap/dfflegalize_dlatch_const.ys index f30a534fd..159692249 100644 --- a/tests/techmap/dfflegalize_dlatch_const.ys +++ b/tests/techmap/dfflegalize_dlatch_const.ys @@ -24,14 +24,14 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DFFSRE_PPPP_ 1 design -load orig dfflegalize -cell $_DFF_PP0_ 01 -select -assert-count 12 t:$_NOT_ +select -assert-count 8 t:$_NOT_ select -assert-count 8 t:$_DFF_PP0_ select -assert-none t:$_DFF_PP0_ t:$_NOT_ %% %n t:* %i design -load orig dfflegalize -cell $_DFF_PP?_ 0 -select -assert-count 12 t:$_NOT_ +select -assert-count 8 t:$_NOT_ select -assert-count 4 t:$_DFF_PP0_ select -assert-count 4 t:$_DFF_PP1_ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i @@ -41,13 +41,13 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_NOT_ %% %n t:* %i design -load orig dfflegalize -cell $_DFFSRE_PPPP_ 0 -select -assert-count 12 t:$_NOT_ +select -assert-count 8 t:$_NOT_ select -assert-count 8 t:$_DFFSRE_PPPP_ select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i design -load orig dfflegalize -cell $_DFFSRE_PPPP_ 1 -select -assert-count 12 t:$_NOT_ +select -assert-count 8 t:$_NOT_ select -assert-count 8 t:$_DFFSRE_PPPP_ select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dlatch_init.ys b/tests/techmap/dfflegalize_dlatch_init.ys index ccc9e41d7..9324c6691 100644 --- a/tests/techmap/dfflegalize_dlatch_init.ys +++ b/tests/techmap/dfflegalize_dlatch_init.ys @@ -16,6 +16,10 @@ equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_PP1_ 1 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 0 equiv_opt -assert -multiclock dfflegalize -cell $_DLATCHSR_PPP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFF_PP_ 1 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 0 +equiv_opt -assert -multiclock dfflegalize -cell $_ALDFFE_PPP_ 1 # Convert everything to DFFs. @@ -80,3 +84,37 @@ dfflegalize -cell $_DLATCHSR_PPP_ 1 select -assert-count 5 t:$_NOT_ select -assert-count 2 t:$_DLATCHSR_PPP_ select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ALDFFs. + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFF_PP_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_ALDFF_PP_ +select -assert-none t:$_ALDFF_PP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ALDFFEs. + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 0 + +select -assert-count 1 t:$_NOT_ +select -assert-count 2 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_ALDFFE_PPP_ 1 + +select -assert-count 5 t:$_NOT_ +select -assert-count 2 t:$_ALDFFE_PPP_ +select -assert-none t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_dlatchsr_init.ys b/tests/techmap/dfflegalize_dlatchsr_init.ys index 2d33634d1..b38a9eb3b 100644 --- a/tests/techmap/dfflegalize_dlatchsr_init.ys +++ b/tests/techmap/dfflegalize_dlatchsr_init.ys @@ -66,8 +66,8 @@ select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_O design -load orig dfflegalize -cell $_DLATCH_PP1_ 0 -select -assert-count 22 dlatchsr0/t:$_NOT_ -select -assert-count 26 dlatchsr1/t:$_NOT_ +select -assert-count 18 dlatchsr0/t:$_NOT_ +select -assert-count 22 dlatchsr1/t:$_NOT_ select -assert-count 4 dlatchsr0/t:$_MUX_ select -assert-count 4 dlatchsr1/t:$_MUX_ select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_ @@ -81,8 +81,8 @@ select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_O design -load orig dfflegalize -cell $_DLATCH_PP1_ 1 -select -assert-count 22 dlatchsr0/t:$_NOT_ -select -assert-count 26 dlatchsr1/t:$_NOT_ +select -assert-count 18 dlatchsr0/t:$_NOT_ +select -assert-count 22 dlatchsr1/t:$_NOT_ select -assert-count 4 dlatchsr0/t:$_MUX_ select -assert-count 4 dlatchsr1/t:$_MUX_ select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_ diff --git a/tests/techmap/dfflegalize_inv.ys b/tests/techmap/dfflegalize_inv.ys index cb42e01a8..a74d74161 100644 --- a/tests/techmap/dfflegalize_inv.ys +++ b/tests/techmap/dfflegalize_inv.ys @@ -2,7 +2,7 @@ read_verilog -icells <<EOT -module top(input C, E, R, S, D, output [64:0] Q); +module top(input C, E, R, S, D, L, AD, output [71:0] Q); $_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0])); $_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1])); @@ -88,16 +88,25 @@ $_SR_PP_ ff62 (.R(R), .S(S), .Q(Q[62])); $_SR_PN_ ff63 (.R(R), .S(S), .Q(Q[63])); $_SR_NP_ ff64 (.R(R), .S(S), .Q(Q[64])); +$_ALDFF_PP_ ff65 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[65])); +$_ALDFF_PN_ ff66 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[66])); +$_ALDFF_NP_ ff67 (.C(C), .L(L), .AD(AD), .D(D), .Q(Q[67])); + +$_ALDFFE_PPP_ ff68 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[68])); +$_ALDFFE_PPN_ ff69 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[69])); +$_ALDFFE_PNP_ ff70 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[70])); +$_ALDFFE_NPP_ ff71 (.C(C), .L(L), .AD(AD), .D(D), .E(E), .Q(Q[71])); + endmodule EOT design -save orig -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x -cell $_ALDFF_PP_ x -cell $_ALDFFE_PPP_ x design -load postopt -select -assert-count 46 t:$_NOT_ +select -assert-count 51 t:$_NOT_ select -assert-count 2 t:$_DFF_P_ select -assert-count 3 t:$_DFFE_PP_ select -assert-count 3 t:$_DFF_PP0_ @@ -117,16 +126,18 @@ select -assert-count 3 t:$_DLATCH_PP0_ select -assert-count 3 t:$_DLATCH_PP1_ select -assert-count 4 t:$_DLATCHSR_PPP_ select -assert-count 3 t:$_SR_PP_ -select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_NOT_ %% %n t:* %i +select -assert-count 3 t:$_ALDFF_PP_ +select -assert-count 4 t:$_ALDFFE_PPP_ +select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_ALDFF_PP_ t:$_ALDFFE_PPP_ t:$_NOT_ %% %n t:* %i # Now try it again, targetting the opposite cells. design -load orig -equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x +equiv_opt -assert -multiclock dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x -cell $_ALDFF_NN_ x -cell $_ALDFFE_NNN_ x design -load postopt -select -assert-count 122 t:$_NOT_ +select -assert-count 135 t:$_NOT_ select -assert-count 2 t:$_DFF_N_ select -assert-count 3 t:$_DFFE_NN_ select -assert-count 3 t:$_DFF_NN0_ @@ -146,7 +157,9 @@ select -assert-count 3 t:$_DLATCH_NN0_ select -assert-count 3 t:$_DLATCH_NN1_ select -assert-count 4 t:$_DLATCHSR_NNN_ select -assert-count 3 t:$_SR_NN_ -select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_NOT_ %% %n t:* %i +select -assert-count 3 t:$_ALDFF_NN_ +select -assert-count 4 t:$_ALDFFE_NNN_ +select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_ALDFF_NN_ t:$_ALDFFE_NNN_ t:$_NOT_ %% %n t:* %i # Second test: make sure set/reset/enable are inverted before clock. diff --git a/tests/techmap/dfflegalize_minsrst.ys b/tests/techmap/dfflegalize_minsrst.ys index 0fc40dc08..689066147 100644 --- a/tests/techmap/dfflegalize_minsrst.ys +++ b/tests/techmap/dfflegalize_minsrst.ys @@ -23,9 +23,9 @@ design -load postopt select -assert-count 5 t:$_SDFF_PP0_ select -assert-count 1 t:$_SDFF_PP1_ -select -assert-count 3 t:$_SDFFE_PP0P_ +select -assert-count 1 t:$_SDFFE_PP0P_ select -assert-count 1 t:$_SDFFE_PP1P_ -select -assert-count 1 t:$_SDFFCE_PP0P_ +select -assert-count 3 t:$_SDFFCE_PP0P_ select -assert-count 1 t:$_SDFFCE_PP1P_ select -assert-count 8 t:$_MUX_ select -assert-count 0 n:ff0 %ci %ci t:$_MUX_ %i diff --git a/tests/techmap/dfflegalize_sr.ys b/tests/techmap/dfflegalize_sr.ys index 27e83be91..ee59a6e3c 100644 --- a/tests/techmap/dfflegalize_sr.ys +++ b/tests/techmap/dfflegalize_sr.ys @@ -39,7 +39,7 @@ select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i design -load orig dfflegalize -cell $_DLATCH_PP1_ x -select -assert-count 8 t:$_NOT_ +select -assert-count 5 t:$_NOT_ select -assert-count 3 t:$_DLATCH_PP1_ select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i diff --git a/tests/techmap/dfflegalize_sr_init.ys b/tests/techmap/dfflegalize_sr_init.ys index 52b797b9e..9d724de29 100644 --- a/tests/techmap/dfflegalize_sr_init.ys +++ b/tests/techmap/dfflegalize_sr_init.ys @@ -12,7 +12,7 @@ $_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1])); $_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2])); endmodule -module top(input C, E, R, D, output [5:0] Q); +module top(input R, S, output [5:0] Q); sr0 sr0_(.S(S), .R(R), .Q(Q[2:0])); sr1 sr1_(.S(S), .R(R), .Q(Q[5:3])); endmodule @@ -103,8 +103,8 @@ select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* design -load orig dfflegalize -cell $_DLATCH_PP1_ 0 -select -assert-count 11 sr0/t:$_NOT_ -select -assert-count 8 sr1/t:$_NOT_ +select -assert-count 8 sr0/t:$_NOT_ +select -assert-count 5 sr1/t:$_NOT_ select -assert-count 3 sr0/t:$_DLATCH_PP1_ select -assert-count 3 sr1/t:$_DLATCH_PP1_ select -assert-count 1 sr0/t:$_ANDNOT_ @@ -118,8 +118,8 @@ select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* design -load orig dfflegalize -cell $_DLATCH_PP1_ 1 -select -assert-count 8 sr0/t:$_NOT_ -select -assert-count 11 sr1/t:$_NOT_ +select -assert-count 5 sr0/t:$_NOT_ +select -assert-count 8 sr1/t:$_NOT_ select -assert-count 3 sr0/t:$_DLATCH_PP1_ select -assert-count 3 sr1/t:$_DLATCH_PP1_ select -assert-count 0 sr0/t:$_ANDNOT_ diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys index df029b3a0..f8e6bc374 100644 --- a/tests/techmap/iopadmap.ys +++ b/tests/techmap/iopadmap.ys @@ -169,7 +169,7 @@ sub s2(.i(i[1]), .o(w[1])); assign o = oe ? w : 2'bz; endmodule -module c(input i, oe, (* init=2'b00 *) inout io, output o1, o2); +module c(input i, oe, (* init=1'b0 *) inout io, output o1, o2); assign io = oe ? i : 1'bz; assign {o1,o2} = {io,io}; endmodule @@ -182,5 +182,5 @@ select -assert-count 1 a/c:s %co a/a:init=1'b1 %i select -assert-count 1 a/a:init select -assert-count 1 b/c:s* %co %a b/a:init=2'b1x %i select -assert-count 1 b/a:init -select -assert-count 1 c/t:iobuf %co c/a:init=2'b00 %i +select -assert-count 1 c/t:iobuf %co c/a:init=1'b0 %i select -assert-count 1 c/a:init diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index 9c41fa56a..b486de5c7 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -2,7 +2,7 @@ set -e -../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'read_verilog mem_simple_4x1_uut.v; proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh index 0725ccf40..564d678fa 100644 --- a/tests/techmap/recursive_runtest.sh +++ b/tests/techmap/recursive_runtest.sh @@ -1,3 +1,3 @@ set -e -../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v +../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys index 1670573dd..bc07f40e6 100644 --- a/tests/techmap/zinit.ys +++ b/tests/techmap/zinit.ys @@ -20,7 +20,8 @@ EOT equiv_opt -assert -multiclock zinit design -load postopt -select -assert-count 20 t:$_NOT_ +select -assert-count 16 t:$_NOT_ +select -assert-count 4 t:$xor select -assert-count 1 w:unused a:init %i select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??1_ %i @@ -52,7 +53,7 @@ design -load postopt select -assert-count 0 t:$_NOT_ select -assert-count 1 w:unused a:init %i -select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i +select -assert-count 1 w:Q a:init=13'bx00x100000000 %i select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??0_ %i select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??1_ %i @@ -142,7 +143,7 @@ EOT zinit select -assert-count 0 t:$_NOT_ -select -assert-count 0 w:Q a:init %i +select -assert-count 1 w:Q a:init=24'b0 %i select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFFE_??0P_ %i select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFFE_??1P_ %i select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$_SDFF_??0_ %i diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 72a3d51eb..e4aef9917 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -197,7 +197,7 @@ do test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext} if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then - "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext} + "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext} $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v fi diff --git a/tests/tools/vcdcd.pl b/tests/tools/vcdcd.pl index 58a92b44d..0f33371fb 100755 --- a/tests/tools/vcdcd.pl +++ b/tests/tools/vcdcd.pl @@ -11,7 +11,7 @@ $| = 1; my $opt_width = 0; my $opt_delay = 0; -while (1) +while ($#ARGV >= 0) { if ($ARGV[0] eq '-w') { $opt_width = +$ARGV[1]; @@ -74,10 +74,10 @@ for my $net (sort keys %gold_signals_hash) { # next unless $net eq "tst_bench_top.i2c_top.byte_controller.bit_controller.cnt"; my %orig_net_names; print "common signal: $net"; - for my $fullname (keys $gold_signals_hash{$net}) { + for my $fullname (keys %{$gold_signals_hash{$net}}) { $orig_net_names{$fullname} = 1; } - for my $fullname (keys $gate_signals_hash{$net}) { + for my $fullname (keys %{$gate_signals_hash{$net}}) { $orig_net_names{$fullname} = 1; } for my $net (sort keys %orig_net_names) { diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index a9880c722..e0add714b 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -90,7 +90,7 @@ $_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z)); endmodule EOT simplemap -equiv_opt abc9 -lut 4 -dff +equiv_opt -assert abc9 -lut 4 -dff design -load postopt cd abc9_test038 select -assert-count 3 t:$_DFF_N_ @@ -99,3 +99,58 @@ clean select -assert-count 2 a:init select -assert-count 1 w:w a:init %i select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i + + +# Check that non-dangling ABC9 black-boxes are preserved +design -reset +read_verilog -specify <<EOT +(* abc9_box, blackbox *) +module mux_with_param(input I0, I1, S, output O); +parameter P = 0; +specify + (I0 => O) = P; + (I1 => O) = P; + (S => O) = P; +endspecify +endmodule + +module abc9_test039(output O); + mux_with_param #(.P(1)) m ( + .I0(1'b1), + .I1(1'b1), + .O(O), + .S(1'b0) + ); +endmodule +EOT +abc9 -lut 4 +cd abc9_test039 +select -assert-count 1 t:mux_with_param + + +# Check that dangling ABC9 black-boxes are swept away +design -reset +read_verilog -specify <<EOT +(* abc9_box, blackbox *) +module mux_with_param(input I0, I1, S, output O); +parameter P = 0; +specify + (I0 => O) = P; + (I1 => O) = P; + (S => O) = P; +endspecify +endmodule + +module abc9_test040(output O); + wire w; + mux_with_param #(.P(1)) m ( + .I0(1'b1), + .I1(1'b1), + .O(w), + .S(1'b0) + ); +endmodule +EOT +abc9 -lut 4 +cd abc9_test040 +select -assert-count 0 t:mux_with_param diff --git a/tests/various/async.sh b/tests/various/async.sh index 7c41d6d94..e83935d02 100644 --- a/tests/various/async.sh +++ b/tests/various/async.sh @@ -1,9 +1,9 @@ #!/bin/bash set -ex -../../yosys -q -o async_syn.v -p 'synth; rename uut syn' async.v -../../yosys -q -o async_prp.v -p 'prep; rename uut prp' async.v -../../yosys -q -o async_a2s.v -p 'prep; async2sync; rename uut a2s' async.v -../../yosys -q -o async_ffl.v -p 'prep; clk2fflogic; rename uut ffl' async.v +../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v +../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v +../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v +../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v iverilog -o async_sim -DTESTBENCH async.v async_???.v vvp -N async_sim > async.out tail async.out diff --git a/tests/various/blackbox_wb.ys b/tests/various/blackbox_wb.ys new file mode 100644 index 000000000..f9c9bec06 --- /dev/null +++ b/tests/various/blackbox_wb.ys @@ -0,0 +1,14 @@ +read_verilog <<EOT +(* whitebox *) +module box(input a, output q); +assign q = ~a; +endmodule + +module top(input a, output q); +box box_i(.a(a), .q(q)); +endmodule +EOT +select -assert-count 1 =box/t:$not +blackbox =box +select -assert-count 0 =A:whitebox +select -assert-count 0 =box/t:$not diff --git a/tests/various/logger_fail.sh b/tests/various/logger_fail.sh new file mode 100755 index 000000000..19b650007 --- /dev/null +++ b/tests/various/logger_fail.sh @@ -0,0 +1,42 @@ +#!/bin/bash + +fail() { + echo "$1" >&2 + exit 1 +} + +runTest() { + desc="$1" + want="$2" + shift 2 + echo "running '$desc' with args $@" + output=`../../yosys -q "$@" 2>&1` + if [ $? -ne 1 ]; then + fail "exit code for '$desc' was not 1" + fi + if [ "$output" != "$want" ]; then + fail "output for '$desc' did not match" + fi +} + +unmet() { + kind=$1 + runTest "unmet $kind" \ + "ERROR: Expected $kind pattern 'foobar' not found !" \ + -p "logger -expect $kind \"foobar\" 1" +} + +unmet log +unmet warning +unmet error + +runTest "too many logs" \ + "ERROR: Expected log pattern 'statistics' found 2 time(s), instead of 1 time(s) !" \ + -p "logger -expect log \"statistics\" 1" -p stat -p stat + +runTest "too many warnings" \ + "Warning: Found log message matching -W regex: +Printing statistics. +ERROR: Expected warning pattern 'statistics' found 2 time(s), instead of 1 time(s) !" \ + -p "logger -warn \"Printing statistics\"" \ + -p "logger -expect warning \"statistics\" 1" -p stat -p stat diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 33ece1f16..752f9ba48 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -154,7 +154,7 @@ always @* o <= i[4*W+:W]; endmodule -module cliffordwolf_nonexclusive_select ( +module clairexen_nonexclusive_select ( input wire x, y, z, input wire a, b, c, d, output reg o @@ -167,7 +167,7 @@ module cliffordwolf_nonexclusive_select ( end endmodule -module cliffordwolf_freduce ( +module clairexen_freduce ( input wire [1:0] s, input wire a, b, c, d, output reg [3:0] o diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 3e90419af..d73fc44b4 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -167,7 +167,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read -hierarchy -top cliffordwolf_nonexclusive_select +hierarchy -top clairexen_nonexclusive_select prep design -save gold muxpack @@ -182,7 +182,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter #design -load read -#hierarchy -top cliffordwolf_freduce +#hierarchy -top clairexen_freduce #prep #design -save gold #proc; opt; freduce; opt diff --git a/tests/various/param_struct.ys b/tests/various/param_struct.ys new file mode 100644 index 000000000..6d7a7c6ad --- /dev/null +++ b/tests/various/param_struct.ys @@ -0,0 +1,51 @@ +read_verilog -sv << EOF +package p; +typedef struct packed { + logic a; + logic b; +} struct_t; + +typedef struct packed { + struct_t g; + logic [2:0] h; +} nested_struct_t; + +typedef union packed { + logic [4:0] x; +} nested_union_t; + +parameter struct_t c = {1'b1, 1'b0}; +parameter nested_struct_t x = {{1'b1, 1'b0}, 1'b1, 1'b1, 1'b1}; +endpackage + +module dut (); +parameter p::struct_t d = p::c; +parameter p::nested_struct_t i = p::x; + +parameter p::nested_union_t u = {5'b11001}; + +localparam e = d.a; +localparam f = d.b; + +localparam j = i.g.a; +localparam k = i.g.b; +localparam l = i.h; +localparam m = i.g; + +localparam o = u.x; + +always_comb begin + assert(d == 2'b10); + assert(e == 1'b1); + assert(f == 1'b0); + assert(j == 1'b1); + assert(k == 1'b0); + assert(l == 3'b111); +// TODO: support access to whole sub-structs and unions +// assert(m == 2'b10); + assert(u == 5'b11001); +end +endmodule +EOF +hierarchy; proc; opt +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/various/sta.ys b/tests/various/sta.ys new file mode 100644 index 000000000..156c31c47 --- /dev/null +++ b/tests/various/sta.ys @@ -0,0 +1,81 @@ +read_verilog -specify <<EOT +module buffer(input i, output o); +specify +(i => o) = 10; +endspecify +endmodule + +module top(input i); +wire w; +buffer b(.i(i), .o(w)); +endmodule +EOT + +logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1 +sta + + +design -reset +read_verilog -specify <<EOT +module top(input i, output o, p); +assign o = i; +endmodule +EOT + +logger -expect log "No timing paths found\." 1 +sta + + +design -reset +read_verilog -specify <<EOT +module buffer(input i, output o); +specify +(i => o) = 10; +endspecify +endmodule + +module top(input i, output o, p); +buffer b(.i(i), .o(o)); +endmodule +EOT + +sta + + +design -reset +read_verilog -specify <<EOT +module buffer(input i, output o); +specify +(i => o) = 10; +endspecify +endmodule + +module top(input i, output o, p); +buffer b(.i(i), .o(o)); +const0 c(.o(p)); +endmodule +EOT + +logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1 +sta + + +design -reset +read_verilog -specify <<EOT +module buffer(input i, output o); +specify +(i => o) = 10; +endspecify +endmodule +module const0(output o); +endmodule + +module top(input i, output o, p); +buffer b(.i(i), .o(o)); +const0 c(.o(p)); +endmodule +EOT + +sta + +logger -expect-no-warnings diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore index 34da23437..96ebe20ba 100644 --- a/tests/verilog/.gitignore +++ b/tests/verilog/.gitignore @@ -3,3 +3,4 @@ /run-test.mk /const_arst.v /const_sr.v +/doubleslash.v diff --git a/tests/verilog/absurd_width.ys b/tests/verilog/absurd_width.ys new file mode 100644 index 000000000..c0d2af4c2 --- /dev/null +++ b/tests/verilog/absurd_width.ys @@ -0,0 +1,17 @@ +logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1 +read_verilog <<EOF +module top( + input inp, + output out +); + assign out = + {1024 { + {1024 { + {1024 { + inp + }} + }} + }} + ; +endmodule +EOF diff --git a/tests/verilog/absurd_width_const.ys b/tests/verilog/absurd_width_const.ys new file mode 100644 index 000000000..b7191fd0d --- /dev/null +++ b/tests/verilog/absurd_width_const.ys @@ -0,0 +1,16 @@ +logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1 +read_verilog <<EOF +module top( + output out +); + assign out = + {1024 { + {1024 { + {1024 { + 1'b1 + }} + }} + }} + ; +endmodule +EOF diff --git a/tests/verilog/always_comb_latch_1.ys b/tests/verilog/always_comb_latch_1.ys new file mode 100644 index 000000000..c98c79fa2 --- /dev/null +++ b/tests/verilog/always_comb_latch_1.ys @@ -0,0 +1,13 @@ +read_verilog -sv <<EOF +module top; +logic x; +always_comb begin + logic y; + if (x) + y = 1; + x = y; +end +endmodule +EOF +logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1 +proc diff --git a/tests/verilog/always_comb_latch_2.ys b/tests/verilog/always_comb_latch_2.ys new file mode 100644 index 000000000..567205a53 --- /dev/null +++ b/tests/verilog/always_comb_latch_2.ys @@ -0,0 +1,15 @@ +read_verilog -sv <<EOF +module top; +logic x; +always_comb begin + logic y; + if (x) + x = 1; + else + y = 1; + x = y; +end +endmodule +EOF +logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1 +proc diff --git a/tests/verilog/always_comb_latch_3.ys b/tests/verilog/always_comb_latch_3.ys new file mode 100644 index 000000000..b9b028ac7 --- /dev/null +++ b/tests/verilog/always_comb_latch_3.ys @@ -0,0 +1,20 @@ +read_verilog -sv <<EOF +module top; +logic x; +logic z; +assign z = 1'b1; +always_comb begin + logic y; + case (x) + 1'b0: + y = 1; + endcase + if (z) + x = y; + else + x = 1'b0; +end +endmodule +EOF +logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1 +proc diff --git a/tests/verilog/always_comb_latch_4.ys b/tests/verilog/always_comb_latch_4.ys new file mode 100644 index 000000000..46b78801b --- /dev/null +++ b/tests/verilog/always_comb_latch_4.ys @@ -0,0 +1,17 @@ +read_verilog -sv <<EOF +module top; +parameter AVOID_LATCH = 0; +logic x, z; +assign z = 1'b1; +always_comb begin + logic y; + if (z) + y = 0; + for (int i = 1; i == AVOID_LATCH; i++) + y = 1; + x = z ? y : 1'b0; +end +endmodule +EOF +logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process" 1 +proc diff --git a/tests/verilog/always_comb_nolatch_1.ys b/tests/verilog/always_comb_nolatch_1.ys new file mode 100644 index 000000000..4d1952b52 --- /dev/null +++ b/tests/verilog/always_comb_nolatch_1.ys @@ -0,0 +1,16 @@ +read_verilog -sv <<EOF +module top; +logic [4:0] x; +logic z; +assign z = 1'b1; +always_comb begin + x = '0; + if (z) begin + for (int i = 0; i < 5; i++) begin + x[i] = 1'b1; + end + end +end +endmodule +EOF +proc diff --git a/tests/verilog/always_comb_nolatch_2.ys b/tests/verilog/always_comb_nolatch_2.ys new file mode 100644 index 000000000..2ec6ca0f4 --- /dev/null +++ b/tests/verilog/always_comb_nolatch_2.ys @@ -0,0 +1,17 @@ +read_verilog -sv <<EOF +module top; +logic [4:0] x; +logic z; +assign z = 1'b1; +always_comb begin + x = '0; + if (z) begin + int i; + for (i = 0; i < 5; i++) begin + x[i] = 1'b1; + end + end +end +endmodule +EOF +proc diff --git a/tests/verilog/always_comb_nolatch_3.ys b/tests/verilog/always_comb_nolatch_3.ys new file mode 100644 index 000000000..33f9833a2 --- /dev/null +++ b/tests/verilog/always_comb_nolatch_3.ys @@ -0,0 +1,21 @@ +read_verilog -sv <<EOF +module top; +logic x; +logic z; +assign z = 1'b1; +always_comb begin + logic y; + case (x) + 1'b0: + y = 1; + default: + y = 0; + endcase + if (z) + x = y; + else + x = 1'b0; +end +endmodule +EOF +proc diff --git a/tests/verilog/always_comb_nolatch_4.ys b/tests/verilog/always_comb_nolatch_4.ys new file mode 100644 index 000000000..bc29b2771 --- /dev/null +++ b/tests/verilog/always_comb_nolatch_4.ys @@ -0,0 +1,16 @@ +read_verilog -sv <<EOF +module top; +parameter AVOID_LATCH = 1; +logic x, z; +assign z = 1'b1; +always_comb begin + logic y; + if (z) + y = 0; + for (int i = 1; i == AVOID_LATCH; i++) + y = 1; + x = z ? y : 1'b0; +end +endmodule +EOF +proc diff --git a/tests/verilog/block_end_label_only.ys b/tests/verilog/block_end_label_only.ys new file mode 100644 index 000000000..5db1c7879 --- /dev/null +++ b/tests/verilog/block_end_label_only.ys @@ -0,0 +1,9 @@ +logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1 +read_verilog -sv <<EOF +module top; +initial + begin + $display("HI"); + end : incorrect_name +endmodule +EOF diff --git a/tests/verilog/block_end_label_wrong.ys b/tests/verilog/block_end_label_wrong.ys new file mode 100644 index 000000000..47dbbe32f --- /dev/null +++ b/tests/verilog/block_end_label_wrong.ys @@ -0,0 +1,9 @@ +logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1 +read_verilog -sv <<EOF +module top; +initial + begin : correct_name + $display("HI"); + end : incorrect_name +endmodule +EOF diff --git a/tests/verilog/doubleslash.ys b/tests/verilog/doubleslash.ys new file mode 100644 index 000000000..c41673ee5 --- /dev/null +++ b/tests/verilog/doubleslash.ys @@ -0,0 +1,21 @@ +read_verilog -sv <<EOT +module doubleslash + (input logic a, + input logic b, + output logic z); + + logic \a//b ; + + assign \a//b = a & b; + assign z = ~\a//b ; + +endmodule : doubleslash +EOT + +hierarchy +proc +opt -full + +write_verilog doubleslash.v +design -reset +read_verilog doubleslash.v diff --git a/tests/verilog/for_decl_no_init.ys b/tests/verilog/for_decl_no_init.ys new file mode 100644 index 000000000..68c1584e0 --- /dev/null +++ b/tests/verilog/for_decl_no_init.ys @@ -0,0 +1,9 @@ +logger -expect error "For loop variable declaration is missing initialization!" 1 +read_verilog -sv <<EOT +module top; + integer z; + initial + for (integer i; i < 10; i = i + 1) + z = i; +endmodule +EOT diff --git a/tests/verilog/for_decl_no_sv.ys b/tests/verilog/for_decl_no_sv.ys new file mode 100644 index 000000000..34edddff7 --- /dev/null +++ b/tests/verilog/for_decl_no_sv.ys @@ -0,0 +1,9 @@ +logger -expect error "For loop inline variable declaration is only supported in SystemVerilog mode!" 1 +read_verilog <<EOT +module top; + integer z; + initial + for (integer i = 1; i < 10; i = i + 1) + z = i; +endmodule +EOT diff --git a/tests/verilog/for_decl_shadow.sv b/tests/verilog/for_decl_shadow.sv new file mode 100644 index 000000000..f6948f97e --- /dev/null +++ b/tests/verilog/for_decl_shadow.sv @@ -0,0 +1,32 @@ +module gate(x); + output reg [15:0] x; + if (1) begin : gen + integer x; + initial begin + for (integer x = 5; x < 10; x++) + if (x == 5) + gen.x = 0; + else + gen.x += 2 ** x; + x = x * 2; + end + end + initial x = gen.x; +endmodule + +module gold(x); + output reg [15:0] x; + if (1) begin : gen + integer x; + integer z; + initial begin + for (z = 5; z < 10; z++) + if (z == 5) + x = 0; + else + x += 2 ** z; + x = x * 2; + end + end + initial x = gen.x; +endmodule diff --git a/tests/verilog/for_decl_shadow.ys b/tests/verilog/for_decl_shadow.ys new file mode 100644 index 000000000..d2dca715e --- /dev/null +++ b/tests/verilog/for_decl_shadow.ys @@ -0,0 +1,6 @@ +read_verilog -sv for_decl_shadow.sv +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/verilog/func_typename_ret.sv b/tests/verilog/func_typename_ret.sv new file mode 100644 index 000000000..423975f97 --- /dev/null +++ b/tests/verilog/func_typename_ret.sv @@ -0,0 +1,35 @@ +typedef logic [1:0] T; + +package P; + typedef logic [3:0] S; +endpackage + +module gate( + output wire [31:0] out1, out2 +); + function automatic T func1; + input reg signed inp; + func1 = inp; + endfunction + assign out1 = func1(1); + function automatic P::S func2; + input reg signed inp; + func2 = inp; + endfunction + assign out2 = func2(1); +endmodule + +module gold( + output wire [31:0] out1, out2 +); + function automatic [1:0] func1; + input reg signed inp; + func1 = inp; + endfunction + assign out1 = func1(1); + function automatic [3:0] func2; + input reg signed inp; + func2 = inp; + endfunction + assign out2 = func2(1); +endmodule diff --git a/tests/verilog/func_typename_ret.ys b/tests/verilog/func_typename_ret.ys new file mode 100644 index 000000000..7f6049961 --- /dev/null +++ b/tests/verilog/func_typename_ret.ys @@ -0,0 +1,5 @@ +read_verilog -sv func_typename_ret.sv +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/verilog/gen_block_end_label_only.ys b/tests/verilog/gen_block_end_label_only.ys new file mode 100644 index 000000000..60dc0476a --- /dev/null +++ b/tests/verilog/gen_block_end_label_only.ys @@ -0,0 +1,9 @@ +logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1 +read_verilog -sv <<EOF +module top; +if (1) + begin + initial $display("HI"); + end : incorrect_name +endmodule +EOF diff --git a/tests/verilog/gen_block_end_label_wrong.ys b/tests/verilog/gen_block_end_label_wrong.ys new file mode 100644 index 000000000..43cfc8773 --- /dev/null +++ b/tests/verilog/gen_block_end_label_wrong.ys @@ -0,0 +1,9 @@ +logger -expect error "Begin label \(correct_name\) and end label \(incorrect_name\) don't match\." 1 +read_verilog -sv <<EOF +module top; +if (1) + begin : correct_name + initial $display("HI"); + end : incorrect_name +endmodule +EOF diff --git a/tests/verilog/genfor_decl_no_init.ys b/tests/verilog/genfor_decl_no_init.ys new file mode 100644 index 000000000..348899195 --- /dev/null +++ b/tests/verilog/genfor_decl_no_init.ys @@ -0,0 +1,7 @@ +logger -expect error "Generate for loop variable declaration is missing initialization!" 1 +read_verilog -sv <<EOT +module top; + for (genvar i; i < 10; i = i + 1) + wire x; +endmodule +EOT diff --git a/tests/verilog/genfor_decl_no_sv.ys b/tests/verilog/genfor_decl_no_sv.ys new file mode 100644 index 000000000..124a27c28 --- /dev/null +++ b/tests/verilog/genfor_decl_no_sv.ys @@ -0,0 +1,7 @@ +logger -expect error "Generate for loop inline variable declaration is only supported in SystemVerilog mode!" 1 +read_verilog <<EOT +module top; + for (genvar i = 1; i < 10; i = i + 1) + wire x; +endmodule +EOT diff --git a/tests/verilog/genvar_loop_decl_1.sv b/tests/verilog/genvar_loop_decl_1.sv new file mode 100644 index 000000000..b503f75da --- /dev/null +++ b/tests/verilog/genvar_loop_decl_1.sv @@ -0,0 +1,18 @@ +`default_nettype none + +module gate(a); + for (genvar i = 0; i < 2; i++) + wire [i:0] x = '1; + + output wire [32:0] a; + assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0}; +endmodule + +module gold(a); + genvar i; + for (i = 0; i < 2; i++) + wire [i:0] x = '1; + + output wire [32:0] a; + assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0}; +endmodule diff --git a/tests/verilog/genvar_loop_decl_1.ys b/tests/verilog/genvar_loop_decl_1.ys new file mode 100644 index 000000000..ded486248 --- /dev/null +++ b/tests/verilog/genvar_loop_decl_1.ys @@ -0,0 +1,14 @@ +read_verilog -sv genvar_loop_decl_1.sv + +select -assert-count 1 gate/genblk1[0].x +select -assert-count 1 gate/genblk1[1].x +select -assert-count 0 gate/genblk1[2].x + +select -assert-count 1 gold/genblk1[0].x +select -assert-count 1 gold/genblk1[1].x +select -assert-count 0 gold/genblk1[2].x + +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/verilog/genvar_loop_decl_2.sv b/tests/verilog/genvar_loop_decl_2.sv new file mode 100644 index 000000000..c5a85ef11 --- /dev/null +++ b/tests/verilog/genvar_loop_decl_2.sv @@ -0,0 +1,30 @@ +`default_nettype none + +module gate(out); + wire [3:0] x; + for (genvar x = 0; x < 2; x++) begin : blk + localparam w = x; + if (x == 0) begin : sub + wire [w:0] x; + end + end + assign x = 2; + assign blk[0].sub.x = '1; + output wire [9:0] out; + assign out = {1'bx, x, blk[0].sub.x}; +endmodule + +module gold(out); + wire [3:0] x; + genvar z; + for (z = 0; z < 2; z++) begin : blk + localparam w = z; + if (z == 0) begin : sub + wire [w:0] x; + end + end + assign x = 2; + assign blk[0].sub.x = '1; + output wire [9:0] out; + assign out = {1'bx, x, blk[0].sub.x}; +endmodule diff --git a/tests/verilog/genvar_loop_decl_2.ys b/tests/verilog/genvar_loop_decl_2.ys new file mode 100644 index 000000000..52fdeb49c --- /dev/null +++ b/tests/verilog/genvar_loop_decl_2.ys @@ -0,0 +1,5 @@ +read_verilog -sv genvar_loop_decl_2.sv +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/verilog/genvar_loop_decl_3.sv b/tests/verilog/genvar_loop_decl_3.sv new file mode 100644 index 000000000..4d6d2366d --- /dev/null +++ b/tests/verilog/genvar_loop_decl_3.sv @@ -0,0 +1,28 @@ +`default_nettype none + +module gate(x, y); + output reg [15:0] x, y; + if (1) begin : gen + integer x, y; + for (genvar x = 0; x < 2; x++) + if (x == 0) + initial gen.x = 10; + assign y = x + 1; + end + initial x = gen.x; + assign y = gen.y; +endmodule + +module gold(x, y); + output reg [15:0] x, y; + if (1) begin : gen + integer x, y; + genvar z; + for (z = 0; z < 2; z++) + if (z == 0) + initial x = 10; + assign y = x + 1; + end + initial x = gen.x; + assign y = gen.y; +endmodule diff --git a/tests/verilog/genvar_loop_decl_3.ys b/tests/verilog/genvar_loop_decl_3.ys new file mode 100644 index 000000000..19f754124 --- /dev/null +++ b/tests/verilog/genvar_loop_decl_3.ys @@ -0,0 +1,5 @@ +read_verilog -sv genvar_loop_decl_3.sv +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/verilog/global_parameter.ys b/tests/verilog/global_parameter.ys new file mode 100644 index 000000000..a7a3cddc7 --- /dev/null +++ b/tests/verilog/global_parameter.ys @@ -0,0 +1,16 @@ +read_verilog -sv <<EOF +parameter P = 1; +module example( + output integer out +); + assign out = P; +endmodule +module top( + output integer out +); + example #(2) e1(out); +endmodule +EOF + +logger -expect error "Can't find object for defparam" 1 +hierarchy diff --git a/tests/verilog/ifdef_nest.ys b/tests/verilog/ifdef_nest.ys new file mode 100644 index 000000000..2202109aa --- /dev/null +++ b/tests/verilog/ifdef_nest.ys @@ -0,0 +1,7 @@ +read_verilog <<EOF +`ifndef a +`ifdef b +`endif +`else +`endif +EOF diff --git a/tests/verilog/ifdef_unterminated.ys b/tests/verilog/ifdef_unterminated.ys new file mode 100644 index 000000000..ce511fa8f --- /dev/null +++ b/tests/verilog/ifdef_unterminated.ys @@ -0,0 +1,4 @@ +logger -expect error "Unterminated preprocessor conditional!" 1 +read_verilog <<EOF +`ifndef a +EOF diff --git a/tests/verilog/localparam_no_default_1.ys b/tests/verilog/localparam_no_default_1.ys new file mode 100644 index 000000000..426a48a1c --- /dev/null +++ b/tests/verilog/localparam_no_default_1.ys @@ -0,0 +1,17 @@ +logger -expect-no-warnings +read_verilog -sv <<EOF +module Module #( + localparam X = 1 +); +endmodule +EOF + +design -reset + +logger -expect error "localparam initialization is missing!" 1 +read_verilog <<EOF +module Module #( + localparam X +); +endmodule +EOF diff --git a/tests/verilog/localparam_no_default_2.ys b/tests/verilog/localparam_no_default_2.ys new file mode 100644 index 000000000..b7b2622ad --- /dev/null +++ b/tests/verilog/localparam_no_default_2.ys @@ -0,0 +1,15 @@ +logger -expect-no-warnings +read_verilog -sv <<EOF +module Module; + localparam X = 1; +endmodule +EOF + +design -reset + +logger -expect error "localparam initialization is missing!" 1 +read_verilog <<EOF +module Module; + localparam X; +endmodule +EOF diff --git a/tests/verilog/macro_arg_tromp.sv b/tests/verilog/macro_arg_tromp.sv new file mode 100644 index 000000000..a9c68a417 --- /dev/null +++ b/tests/verilog/macro_arg_tromp.sv @@ -0,0 +1,21 @@ +// Taken from: https://github.com/YosysHQ/yosys/issues/2867 + +`define MIN(x, y) ((x) < (y) ? (x) : (y)) +`define CEIL_DIV(x, y) (((x) / (y)) + `MIN((x) % (y), 1)) + +module pad_msg1 (input logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] x, + output logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] y); + assign y[63:0] = x; +endmodule + +module pad_msg2 (input logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] x, + output logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] y); + assign y[63:0] = x; +endmodule + +module top(...); +`define add(x) x + +input [3:0] A; +output [3:0] B; +assign B = `add(`add(3)A)A; +endmodule diff --git a/tests/verilog/macro_arg_tromp.ys b/tests/verilog/macro_arg_tromp.ys new file mode 100644 index 000000000..e8bd58e9b --- /dev/null +++ b/tests/verilog/macro_arg_tromp.ys @@ -0,0 +1,2 @@ +logger -expect-no-warnings +read_verilog -sv macro_arg_tromp.sv diff --git a/tests/verilog/mem_bounds.sv b/tests/verilog/mem_bounds.sv new file mode 100644 index 000000000..7fb2fb042 --- /dev/null +++ b/tests/verilog/mem_bounds.sv @@ -0,0 +1,27 @@ +module top; + reg [0:7] mem [0:2]; + + initial mem[1] = '1; + wire [31:0] a, b, c, d; + assign a = mem[1]; + assign b = mem[-1]; + assign c = mem[-1][0]; + assign d = mem[-1][0:1]; + + always @* begin + + assert ($countbits(a, '0) == 24); + assert ($countbits(a, '1) == 8); + assert ($countbits(a, 'x) == 0); + + assert ($countbits(b, '0) == 24); + assert ($countbits(b, 'x) == 8); + + assert ($countbits(c, '0) == 31); + assert ($countbits(c, 'x) == 1); + + assert ($countbits(d, '0) == 30); + assert ($countbits(d, 'x) == 2); + + end +endmodule diff --git a/tests/verilog/mem_bounds.ys b/tests/verilog/mem_bounds.ys new file mode 100644 index 000000000..42623ad09 --- /dev/null +++ b/tests/verilog/mem_bounds.ys @@ -0,0 +1,6 @@ +read_verilog -sv -mem2reg mem_bounds.sv +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef diff --git a/tests/verilog/module_end_label.ys b/tests/verilog/module_end_label.ys new file mode 100644 index 000000000..c9e5a13a2 --- /dev/null +++ b/tests/verilog/module_end_label.ys @@ -0,0 +1,15 @@ +logger -expect-no-warnings +read_verilog -sv <<EOF +module correct_name; +localparam X = 1; +endmodule : correct_name +EOF + +design -reset + +logger -expect error "Module name \(correct_name\) and end label \(incorrect_name\) don't match\." 1 +read_verilog -sv <<EOF +module correct_name; +localparam X = 1; +endmodule : incorrect_name +EOF diff --git a/tests/verilog/net_types.sv b/tests/verilog/net_types.sv new file mode 100644 index 000000000..7226a7ee5 --- /dev/null +++ b/tests/verilog/net_types.sv @@ -0,0 +1,34 @@ +module top; + wire logic wire_logic_0; assign wire_logic_0 = 0; + wire logic wire_logic_1; assign wire_logic_1 = 1; + wand logic wand_logic_0; assign wand_logic_0 = 0; assign wand_logic_0 = 1; + wand logic wand_logic_1; assign wand_logic_1 = 1; assign wand_logic_1 = 1; + wor logic wor_logic_0; assign wor_logic_0 = 0; assign wor_logic_0 = 0; + wor logic wor_logic_1; assign wor_logic_1 = 1; assign wor_logic_1 = 0; + + wire integer wire_integer; assign wire_integer = 4'b1001; + wand integer wand_integer; assign wand_integer = 4'b1001; assign wand_integer = 4'b1010; + wor integer wor_integer; assign wor_integer = 4'b1001; assign wor_integer = 4'b1010; + + typedef logic [3:0] typename; + wire typename wire_typename; assign wire_typename = 4'b1001; + wand typename wand_typename; assign wand_typename = 4'b1001; assign wand_typename = 4'b1010; + wor typename wor_typename; assign wor_typename = 4'b1001; assign wor_typename = 4'b1010; + + always @* begin + assert (wire_logic_0 == 0); + assert (wire_logic_1 == 1); + assert (wand_logic_0 == 0); + assert (wand_logic_1 == 1); + assert (wor_logic_0 == 0); + assert (wor_logic_1 == 1); + + assert (wire_integer == 4'b1001); + assert (wand_integer == 4'b1000); + assert (wor_integer == 4'b1011); + + assert (wire_typename == 4'b1001); + assert (wand_typename == 4'b1000); + assert (wor_typename == 4'b1011); + end +endmodule diff --git a/tests/verilog/net_types.ys b/tests/verilog/net_types.ys new file mode 100644 index 000000000..9f75812ea --- /dev/null +++ b/tests/verilog/net_types.ys @@ -0,0 +1,5 @@ +read_verilog -sv net_types.sv +hierarchy +proc +opt -full +sat -verify -prove-asserts -show-all diff --git a/tests/verilog/package_end_label.ys b/tests/verilog/package_end_label.ys new file mode 100644 index 000000000..ccc5c96e9 --- /dev/null +++ b/tests/verilog/package_end_label.ys @@ -0,0 +1,15 @@ +logger -expect-no-warnings +read_verilog -sv <<EOF +package correct_name; +localparam X = 1; +endpackage : correct_name +EOF + +design -reset + +logger -expect error "Package name \(correct_name\) and end label \(incorrect_name\) don't match\." 1 +read_verilog -sv <<EOF +package correct_name; +localparam X = 1; +endpackage : incorrect_name +EOF diff --git a/tests/verilog/package_task_func.sv b/tests/verilog/package_task_func.sv new file mode 100644 index 000000000..2df7a5205 --- /dev/null +++ b/tests/verilog/package_task_func.sv @@ -0,0 +1,30 @@ +package P; + localparam Y = 2; + localparam X = Y + 1; + task t; + output integer x; + x = Y; + endtask + function automatic integer f; + input integer i; + f = i * X; + endfunction + function automatic integer g; + input integer i; + g = i == 0 ? 1 : Y * g(i - 1); + endfunction + localparam Z = g(4); +endpackage + +module top; + integer a; + initial P::t(a); + integer b = P::f(3); + integer c = P::g(3); + integer d = P::Z; + + assert property (a == 2); + assert property (b == 9); + assert property (c == 8); + assert property (d == 16); +endmodule diff --git a/tests/verilog/package_task_func.ys b/tests/verilog/package_task_func.ys new file mode 100644 index 000000000..c94cc2acb --- /dev/null +++ b/tests/verilog/package_task_func.ys @@ -0,0 +1,4 @@ +read_verilog -sv package_task_func.sv +proc +opt -full +sat -verify -seq 1 -prove-asserts -show-all diff --git a/tests/verilog/param_no_default.sv b/tests/verilog/param_no_default.sv new file mode 100644 index 000000000..cc35bd2ea --- /dev/null +++ b/tests/verilog/param_no_default.sv @@ -0,0 +1,52 @@ +module example #( + parameter w, + parameter x = 1, + parameter byte y, + parameter byte z = 3 +) ( + output a, b, + output byte c, d +); + assign a = w; + assign b = x; + assign c = y; + assign d = z; +endmodule + +module top; + wire a1, b1; + wire a2, b2; + wire a3, b3; + wire a4, b4; + byte c1, d1; + byte c2, d2; + byte c3, d3; + byte c4, d4; + + example #(0, 1, 2) e1(a1, b1, c1, d1); + example #(.w(1), .y(4)) e2(a2, b2, c2, d2); + example #(.x(0), .w(1), .y(5)) e3(a3, b3, c3, d3); + example #(1, 0, 9, 10) e4(a4, b4, c4, d4); + + always @* begin + assert (a1 == 0); + assert (b1 == 1); + assert (c1 == 2); + assert (d1 == 3); + + assert (a2 == 1); + assert (b2 == 1); + assert (c2 == 4); + assert (d3 == 3); + + assert (a3 == 1); + assert (b3 == 0); + assert (c3 == 5); + assert (d3 == 3); + + assert (a4 == 1); + assert (b4 == 0); + assert (c4 == 9); + assert (d4 == 10); + end +endmodule diff --git a/tests/verilog/param_no_default.ys b/tests/verilog/param_no_default.ys new file mode 100644 index 000000000..7f161a909 --- /dev/null +++ b/tests/verilog/param_no_default.ys @@ -0,0 +1,7 @@ +read_verilog -sv param_no_default.sv +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/param_no_default_not_svmode.ys b/tests/verilog/param_no_default_not_svmode.ys new file mode 100644 index 000000000..1ded84e9c --- /dev/null +++ b/tests/verilog/param_no_default_not_svmode.ys @@ -0,0 +1,26 @@ +logger -expect-no-warnings +read_verilog -sv <<EOF +module Module; + parameter X; +endmodule +EOF + +design -reset + +logger -expect-no-warnings +read_verilog -sv <<EOF +module Module #( + parameter X +); +endmodule +EOF + +design -reset + +logger -expect error "Parameter defaults can only be omitted in SystemVerilog mode!" 1 +read_verilog <<EOF +module Module #( + parameter X +); +endmodule +EOF diff --git a/tests/verilog/param_no_default_unbound_1.ys b/tests/verilog/param_no_default_unbound_1.ys new file mode 100644 index 000000000..4aab85ab5 --- /dev/null +++ b/tests/verilog/param_no_default_unbound_1.ys @@ -0,0 +1,12 @@ +read_verilog -sv <<EOF +module Example #( + parameter X +); +endmodule +module top; + Example e(); +endmodule +EOF + +logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1 +hierarchy -top top diff --git a/tests/verilog/param_no_default_unbound_2.ys b/tests/verilog/param_no_default_unbound_2.ys new file mode 100644 index 000000000..4b7f3b028 --- /dev/null +++ b/tests/verilog/param_no_default_unbound_2.ys @@ -0,0 +1,12 @@ +read_verilog -sv <<EOF +module Example #( + parameter X, Y +); +endmodule +module top; + Example e(); +endmodule +EOF + +logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1 +hierarchy -top top diff --git a/tests/verilog/param_no_default_unbound_3.ys b/tests/verilog/param_no_default_unbound_3.ys new file mode 100644 index 000000000..f32b879a5 --- /dev/null +++ b/tests/verilog/param_no_default_unbound_3.ys @@ -0,0 +1,12 @@ +read_verilog -sv <<EOF +module Example #( + parameter X, Y +); +endmodule +module top; + Example #(1) e(); +endmodule +EOF + +logger -expect error "Parameter `\\Y' has no default value and has not been overridden!" 1 +hierarchy -top top diff --git a/tests/verilog/param_no_default_unbound_4.ys b/tests/verilog/param_no_default_unbound_4.ys new file mode 100644 index 000000000..3a8d69d78 --- /dev/null +++ b/tests/verilog/param_no_default_unbound_4.ys @@ -0,0 +1,12 @@ +read_verilog -sv <<EOF +module Example #( + parameter X, Y +); +endmodule +module top; + Example #(.Y(1)) e(); +endmodule +EOF + +logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1 +hierarchy -top top diff --git a/tests/verilog/param_no_default_unbound_5.ys b/tests/verilog/param_no_default_unbound_5.ys new file mode 100644 index 000000000..30282eba7 --- /dev/null +++ b/tests/verilog/param_no_default_unbound_5.ys @@ -0,0 +1,12 @@ +read_verilog -sv <<EOF +module Example #( + parameter X, Y = 2 +); +endmodule +module top; + Example #(.Y(1)) e(); +endmodule +EOF + +logger -expect error "Parameter `\\X' has no default value and has not been overridden!" 1 +hierarchy -top top diff --git a/tests/verilog/parameters_across_files.ys b/tests/verilog/parameters_across_files.ys new file mode 100644 index 000000000..c53e40179 --- /dev/null +++ b/tests/verilog/parameters_across_files.ys @@ -0,0 +1,20 @@ +read_verilog -sv <<EOF +parameter Q = 1; +EOF +read_verilog -sv <<EOF +parameter P = Q; +module top( + output integer out +); + assign out = P; + always @* + assert (out == 1); +endmodule +EOF + +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/prefix.sv b/tests/verilog/prefix.sv new file mode 100644 index 000000000..2d7fbb134 --- /dev/null +++ b/tests/verilog/prefix.sv @@ -0,0 +1,95 @@ +module top; + genvar i, j; + if (1) begin : blk1 + integer a = 1; + for (i = 0; i < 2; i = i + 1) begin : blk2 + integer b = i; + for (j = 0; j < 2; j = j + 1) begin : blk3 + integer c = j; + localparam x = i; + localparam y = j; + always @* begin + assert (1 == a); + assert (1 == blk1.a); + assert (1 == top.blk1.a); + assert (i == b); + assert (i == blk2[i].b); + assert (i == blk1.blk2[i].b); + assert (i == top.blk1.blk2[i].b); + assert (i == blk2[x].b); + assert (i == blk1.blk2[x].b); + assert (i == top.blk1.blk2[x].b); + assert (j == c); + assert (j == blk3[j].c); + assert (j == blk2[x].blk3[j].c); + assert (j == blk1.blk2[x].blk3[j].c); + assert (j == top.blk1.blk2[x].blk3[j].c); + assert (j == c); + assert (j == blk3[y].c); + assert (j == blk2[x].blk3[y].c); + assert (j == blk1.blk2[x].blk3[y].c); + assert (j == top.blk1.blk2[x].blk3[y].c); + assert (j == top.blk1.blk2[x].blk3[y].c[0]); + assert (0 == top.blk1.blk2[x].blk3[y].c[1]); + assert (0 == top.blk1.blk2[x].blk3[y].c[j]); + end + end + always @* begin + assert (1 == a); + assert (1 == blk1.a); + assert (1 == top.blk1.a); + assert (i == b); + assert (i == blk2[i].b); + assert (i == blk1.blk2[i].b); + assert (i == top.blk1.blk2[i].b); + assert (0 == blk3[0].c); + assert (0 == blk2[i].blk3[0].c); + assert (0 == blk1.blk2[i].blk3[0].c); + assert (0 == top.blk1.blk2[i].blk3[0].c); + assert (1 == blk3[1].c); + assert (1 == blk2[i].blk3[1].c); + assert (1 == blk1.blk2[i].blk3[1].c); + assert (1 == top.blk1.blk2[i].blk3[1].c); + end + end + always @* begin + assert (1 == a); + assert (1 == blk1.a); + assert (1 == top.blk1.a); + assert (0 == blk2[0].b); + assert (0 == blk1.blk2[0].b); + assert (0 == top.blk1.blk2[0].b); + assert (1 == blk2[1].b); + assert (1 == blk1.blk2[1].b); + assert (1 == top.blk1.blk2[1].b); + assert (0 == blk2[0].blk3[0].c); + assert (0 == blk1.blk2[0].blk3[0].c); + assert (0 == top.blk1.blk2[0].blk3[0].c); + assert (1 == blk2[0].blk3[1].c); + assert (1 == blk1.blk2[0].blk3[1].c); + assert (1 == top.blk1.blk2[0].blk3[1].c); + assert (0 == blk2[1].blk3[0].c); + assert (0 == blk1.blk2[1].blk3[0].c); + assert (0 == top.blk1.blk2[1].blk3[0].c); + assert (1 == blk2[1].blk3[1].c); + assert (1 == blk1.blk2[1].blk3[1].c); + assert (1 == top.blk1.blk2[1].blk3[1].c); + end + end + always @* begin + assert (1 == blk1.a); + assert (1 == top.blk1.a); + assert (0 == blk1.blk2[0].b); + assert (0 == top.blk1.blk2[0].b); + assert (1 == blk1.blk2[1].b); + assert (1 == top.blk1.blk2[1].b); + assert (0 == blk1.blk2[0].blk3[0].c); + assert (0 == top.blk1.blk2[0].blk3[0].c); + assert (1 == blk1.blk2[0].blk3[1].c); + assert (1 == top.blk1.blk2[0].blk3[1].c); + assert (0 == blk1.blk2[1].blk3[0].c); + assert (0 == top.blk1.blk2[1].blk3[0].c); + assert (1 == blk1.blk2[1].blk3[1].c); + assert (1 == top.blk1.blk2[1].blk3[1].c); + end +endmodule diff --git a/tests/verilog/prefix.ys b/tests/verilog/prefix.ys new file mode 100644 index 000000000..ed3b3a111 --- /dev/null +++ b/tests/verilog/prefix.ys @@ -0,0 +1,5 @@ +read_verilog -sv prefix.sv +hierarchy +proc +select -module top +sat -verify -seq 1 -prove-asserts -show-all diff --git a/tests/verilog/size_cast.sv b/tests/verilog/size_cast.sv new file mode 100644 index 000000000..1636f8d70 --- /dev/null +++ b/tests/verilog/size_cast.sv @@ -0,0 +1,140 @@ +module top; + logic L1b0 = 0; + logic L1b1 = 1; + + logic signed L1sb0 = 0; + logic signed L1sb1 = 1; + + logic [1:0] L2b00 = 0; + logic [1:0] L2b01 = 1; + logic [1:0] L2b10 = 2; + logic [1:0] L2b11 = 3; + + logic signed [1:0] L2sb00 = 0; + logic signed [1:0] L2sb01 = 1; + logic signed [1:0] L2sb10 = 2; + logic signed [1:0] L2sb11 = 3; + + logic y = 1; + + always @* begin + + assert (1'(L1b0 ) == 1'b0); + assert (1'(L1b1 ) == 1'b1); + assert (1'(L1sb0 ) == 1'b0); + assert (1'(L1sb1 ) == 1'b1); + assert (1'(L2b00 ) == 1'b0); + assert (1'(L2b01 ) == 1'b1); + assert (1'(L2b10 ) == 1'b0); + assert (1'(L2b11 ) == 1'b1); + assert (1'(L2sb00) == 1'b0); + assert (1'(L2sb01) == 1'b1); + assert (1'(L2sb10) == 1'b0); + assert (1'(L2sb11) == 1'b1); + + assert (2'(L1b0 ) == 2'b00); + assert (2'(L1b1 ) == 2'b01); + assert (2'(L1sb0 ) == 2'b00); + assert (2'(L1sb1 ) == 2'b11); + assert (2'(L2b00 ) == 2'b00); + assert (2'(L2b01 ) == 2'b01); + assert (2'(L2b10 ) == 2'b10); + assert (2'(L2b11 ) == 2'b11); + assert (2'(L2sb00) == 2'b00); + assert (2'(L2sb01) == 2'b01); + assert (2'(L2sb10) == 2'b10); + assert (2'(L2sb11) == 2'b11); + + assert (3'(L1b0 ) == 3'b000); + assert (3'(L1b1 ) == 3'b001); + assert (3'(L1sb0 ) == 3'b000); + assert (3'(L1sb1 ) == 3'b111); + assert (3'(L2b00 ) == 3'b000); + assert (3'(L2b01 ) == 3'b001); + assert (3'(L2b10 ) == 3'b010); + assert (3'(L2b11 ) == 3'b011); + assert (3'(L2sb00) == 3'b000); + assert (3'(L2sb01) == 3'b001); + assert (3'(L2sb10) == 3'b110); + assert (3'(L2sb11) == 3'b111); + + assert (3'(L1b0 | '1) == 3'b111); + assert (3'(L1b1 | '1) == 3'b111); + assert (3'(L1sb0 | '1) == 3'b111); + assert (3'(L1sb1 | '1) == 3'b111); + assert (3'(L2b00 | '1) == 3'b111); + assert (3'(L2b01 | '1) == 3'b111); + assert (3'(L2b10 | '1) == 3'b111); + assert (3'(L2b11 | '1) == 3'b111); + assert (3'(L2sb00 | '1) == 3'b111); + assert (3'(L2sb01 | '1) == 3'b111); + assert (3'(L2sb10 | '1) == 3'b111); + assert (3'(L2sb11 | '1) == 3'b111); + + assert (3'(L1b0 | '0) == 3'b000); + assert (3'(L1b1 | '0) == 3'b001); + assert (3'(L1sb0 | '0) == 3'b000); + assert (3'(L1sb1 | '0) == 3'b001); + assert (3'(L2b00 | '0) == 3'b000); + assert (3'(L2b01 | '0) == 3'b001); + assert (3'(L2b10 | '0) == 3'b010); + assert (3'(L2b11 | '0) == 3'b011); + assert (3'(L2sb00 | '0) == 3'b000); + assert (3'(L2sb01 | '0) == 3'b001); + assert (3'(L2sb10 | '0) == 3'b010); + assert (3'(L2sb11 | '0) == 3'b011); + + assert (3'(y ? L1b0 : '1) == 3'b000); + assert (3'(y ? L1b1 : '1) == 3'b001); + assert (3'(y ? L1sb0 : '1) == 3'b000); + assert (3'(y ? L1sb1 : '1) == 3'b001); + assert (3'(y ? L2b00 : '1) == 3'b000); + assert (3'(y ? L2b01 : '1) == 3'b001); + assert (3'(y ? L2b10 : '1) == 3'b010); + assert (3'(y ? L2b11 : '1) == 3'b011); + assert (3'(y ? L2sb00 : '1) == 3'b000); + assert (3'(y ? L2sb01 : '1) == 3'b001); + assert (3'(y ? L2sb10 : '1) == 3'b010); + assert (3'(y ? L2sb11 : '1) == 3'b011); + + assert (3'(y ? L1b0 : '0) == 3'b000); + assert (3'(y ? L1b1 : '0) == 3'b001); + assert (3'(y ? L1sb0 : '0) == 3'b000); + assert (3'(y ? L1sb1 : '0) == 3'b001); + assert (3'(y ? L2b00 : '0) == 3'b000); + assert (3'(y ? L2b01 : '0) == 3'b001); + assert (3'(y ? L2b10 : '0) == 3'b010); + assert (3'(y ? L2b11 : '0) == 3'b011); + assert (3'(y ? L2sb00 : '0) == 3'b000); + assert (3'(y ? L2sb01 : '0) == 3'b001); + assert (3'(y ? L2sb10 : '0) == 3'b010); + assert (3'(y ? L2sb11 : '0) == 3'b011); + + assert (3'(y ? L1b0 : 1'sb0) == 3'b000); + assert (3'(y ? L1b1 : 1'sb0) == 3'b001); + assert (3'(y ? L1sb0 : 1'sb0) == 3'b000); + assert (3'(y ? L1sb1 : 1'sb0) == 3'b111); + assert (3'(y ? L2b00 : 1'sb0) == 3'b000); + assert (3'(y ? L2b01 : 1'sb0) == 3'b001); + assert (3'(y ? L2b10 : 1'sb0) == 3'b010); + assert (3'(y ? L2b11 : 1'sb0) == 3'b011); + assert (3'(y ? L2sb00 : 1'sb0) == 3'b000); + assert (3'(y ? L2sb01 : 1'sb0) == 3'b001); + assert (3'(y ? L2sb10 : 1'sb0) == 3'b110); + assert (3'(y ? L2sb11 : 1'sb0) == 3'b111); + + assert (3'(y ? L1b0 : 1'sb1) == 3'b000); + assert (3'(y ? L1b1 : 1'sb1) == 3'b001); + assert (3'(y ? L1sb0 : 1'sb1) == 3'b000); + assert (3'(y ? L1sb1 : 1'sb1) == 3'b111); + assert (3'(y ? L2b00 : 1'sb1) == 3'b000); + assert (3'(y ? L2b01 : 1'sb1) == 3'b001); + assert (3'(y ? L2b10 : 1'sb1) == 3'b010); + assert (3'(y ? L2b11 : 1'sb1) == 3'b011); + assert (3'(y ? L2sb00 : 1'sb1) == 3'b000); + assert (3'(y ? L2sb01 : 1'sb1) == 3'b001); + assert (3'(y ? L2sb10 : 1'sb1) == 3'b110); + assert (3'(y ? L2sb11 : 1'sb1) == 3'b111); + + end +endmodule diff --git a/tests/verilog/size_cast.ys b/tests/verilog/size_cast.ys new file mode 100644 index 000000000..6890cd2d5 --- /dev/null +++ b/tests/verilog/size_cast.ys @@ -0,0 +1,5 @@ +read_verilog -sv size_cast.sv +proc +opt -full +select -module top +sat -verify -prove-asserts -show-all diff --git a/tests/verilog/struct_access.sv b/tests/verilog/struct_access.sv new file mode 100644 index 000000000..f13b8dd51 --- /dev/null +++ b/tests/verilog/struct_access.sv @@ -0,0 +1,88 @@ +module top; + + typedef struct packed { + logic a; + logic signed b; + byte c; + byte unsigned d; + reg [3:0] e; + reg signed [3:0] f; + struct packed { + logic a; + logic signed b; + } x; + struct packed signed { + logic a; + logic signed b; + } y; + } S; + S s; + + initial begin + // test codegen for LHS + s.a = '1; + s.b = '1; + s.c = '1; + s.d = '1; + s.e = '1; + s.f = '1; + s.x.a = '1; + s.x.b = '1; + s.y.a = '1; + s.y.b = '1; + end + +`define CHECK(expr, width, signedness) \ + case (expr) \ + 1'sb1: \ + case (expr) \ + 2'sb11: if (!(signedness)) fail = 1; \ + default: if (signedness) fail = 1; \ + endcase \ + default: if (signedness) fail = 1; \ + endcase \ + case (expr) \ + 1'b1: if ((width) != 1) fail = 1; \ + 2'b11: if ((width) != 2) fail = 1; \ + 3'b111: if ((width) != 3) fail = 1; \ + 4'b1111: if ((width) != 4) fail = 1; \ + 5'b1111_1: if ((width) != 5) fail = 1; \ + 6'b1111_11: if ((width) != 6) fail = 1; \ + 7'b1111_11: if ((width) != 7) fail = 1; \ + 8'b1111_1111: if ((width) != 8) fail = 1; \ + 9'b1111_1111_1: if ((width) != 9) fail = 1; \ + default: fail = 1; \ + endcase \ + begin \ + reg [9:0] indirect; \ + indirect = (expr); \ + if ((indirect != (expr)) != (signedness)) fail = 1; \ + indirect = $unsigned(expr); \ + if ($countones(indirect) != (width)) fail = 1; \ + end + + initial begin + reg fail; + fail = 0; + + `CHECK(s.a, 1, 0) + `CHECK(s.b, 1, 1) + `CHECK(s.c, 8, 1) + `CHECK(s.d, 8, 0) + `CHECK(s.e, 4, 0) + `CHECK(s.f, 4, 1) + + `CHECK(s.x.a, 1, 0) + `CHECK(s.x.b, 1, 1) + `CHECK(s.y.a, 1, 0) + `CHECK(s.y.b, 1, 1) + + // TODO(zachjs): support access to whole sub-structs and unions + // `CHECK(s.x, 2, 0) + // `CHECK(s.y, 2, 1) + + assert (fail === 0); + end + + +endmodule diff --git a/tests/verilog/struct_access.ys b/tests/verilog/struct_access.ys new file mode 100644 index 000000000..29d569c01 --- /dev/null +++ b/tests/verilog/struct_access.ys @@ -0,0 +1,4 @@ +read_verilog -formal -sv struct_access.sv +proc +opt -full +sat -verify -seq 1 -prove-asserts -show-all diff --git a/tests/verilog/typedef_across_files.ys b/tests/verilog/typedef_across_files.ys new file mode 100644 index 000000000..ca9bba736 --- /dev/null +++ b/tests/verilog/typedef_across_files.ys @@ -0,0 +1,23 @@ +read_verilog -sv <<EOF +typedef logic T; +EOF + +read_verilog -sv <<EOF +typedef T [3:0] S; +EOF + +read_verilog -sv <<EOF +module top; + T t; + S s; + always @* begin + assert ($bits(t) == 1); + assert ($bits(s) == 4); + end +endmodule +EOF + +proc +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/typedef_legacy_conflict.ys b/tests/verilog/typedef_legacy_conflict.ys new file mode 100644 index 000000000..8dff4ec5f --- /dev/null +++ b/tests/verilog/typedef_legacy_conflict.ys @@ -0,0 +1,37 @@ +read_verilog -sv <<EOF +typedef logic T; +typedef T [3:0] S; +EOF + +read_verilog -sv <<EOF +module example; + // S and T refer to the definitions from the first file + T t; + S s; + always @* begin + assert ($bits(t) == 1); + assert ($bits(s) == 4); + end +endmodule + +typedef byte T; +typedef T S; + +module top; + // S and T refer to the most recent overrides + T t; + S s; + always @* begin + assert ($bits(t) == 8); + assert ($bits(s) == 8); + end + example e(); +endmodule +EOF + +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/unbased_unsized.sv b/tests/verilog/unbased_unsized.sv new file mode 100644 index 000000000..1d0c5a72c --- /dev/null +++ b/tests/verilog/unbased_unsized.sv @@ -0,0 +1,40 @@ +module pass_through( + input [63:0] inp, + output [63:0] out +); + assign out = inp; +endmodule + +module top; + logic [63:0] + o01, o02, o03, o04, + o05, o06, o07, o08, + o09, o10, o11, o12, + o13, o14, o15, o16; + assign o01 = '0; + assign o02 = '1; + assign o03 = 'x; + assign o04 = 'z; + assign o05 = 3'('0); + assign o06 = 3'('1); + assign o07 = 3'('x); + assign o08 = 3'('z); + pass_through pt09('0, o09); + pass_through pt10('1, o10); + pass_through pt11('x, o11); + pass_through pt12('z, o12); + always @* begin + assert (o01 === {64 {1'b0}}); + assert (o02 === {64 {1'b1}}); + assert (o03 === {64 {1'bx}}); + assert (o04 === {64 {1'bz}}); + assert (o05 === {61'b0, 3'b000}); + assert (o06 === {61'b0, 3'b111}); + assert (o07 === {61'b0, 3'bxxx}); + assert (o08 === {61'b0, 3'bzzz}); + assert (o09 === {64 {1'b0}}); + assert (o10 === {64 {1'b1}}); + assert (o11 === {64 {1'bx}}); + assert (o12 === {64 {1'bz}}); + end +endmodule diff --git a/tests/verilog/unbased_unsized.ys b/tests/verilog/unbased_unsized.ys new file mode 100644 index 000000000..e1bc99c64 --- /dev/null +++ b/tests/verilog/unbased_unsized.ys @@ -0,0 +1,7 @@ +read_verilog -sv unbased_unsized.sv +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/unbased_unsized_tern.sv b/tests/verilog/unbased_unsized_tern.sv new file mode 100644 index 000000000..ad8493394 --- /dev/null +++ b/tests/verilog/unbased_unsized_tern.sv @@ -0,0 +1,31 @@ +module pass_through #( + parameter WIDTH = 1 +) ( + input logic [WIDTH-1:0] inp, + output logic [WIDTH-1:0] out +); + assign out = inp; +endmodule + +module gate ( + input logic inp, + output logic [63:0] + out1, out2, out3, out4 +); + pass_through #(40) pt1('1, out1); + pass_through #(40) pt2(inp ? '1 : '0, out2); + pass_through #(40) pt3(inp ? '1 : 2'b10, out3); + pass_through #(40) pt4(inp ? '1 : inp, out4); +endmodule + +module gold ( + input logic inp, + output logic [63:0] + out1, out2, out3, out4 +); + localparam ONES = 40'hFF_FFFF_FFFF; + pass_through #(40) pt1(ONES, out1); + pass_through #(40) pt2(inp ? ONES : 0, out2); + pass_through #(40) pt3(inp ? ONES : 2'sb10, out3); + pass_through #(40) pt4(inp ? ONES : inp, out4); +endmodule diff --git a/tests/verilog/unbased_unsized_tern.ys b/tests/verilog/unbased_unsized_tern.ys new file mode 100644 index 000000000..5ef63c559 --- /dev/null +++ b/tests/verilog/unbased_unsized_tern.ys @@ -0,0 +1,6 @@ +read_verilog -sv unbased_unsized_tern.sv +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/verilog/unmatched_endif_2.ys b/tests/verilog/unmatched_endif_2.ys new file mode 100644 index 000000000..2ee084170 --- /dev/null +++ b/tests/verilog/unmatched_endif_2.ys @@ -0,0 +1,7 @@ +logger -expect error "Found `endif outside of macro conditional branch!" 1 +read_verilog <<EOF +`ifndef a +`else +`endif +`endif +EOF diff --git a/tests/vloghtb/run-test.sh b/tests/vloghtb/run-test.sh index ad99226e7..3c0689619 100755 --- a/tests/vloghtb/run-test.sh +++ b/tests/vloghtb/run-test.sh @@ -3,7 +3,7 @@ set -ex rm -rf Makefile refdat rtl scripts spec -wget -N http://www.clifford.at/yosys/nogit/vloghammer_tb.tar.bz2 +wget -N https://yosyshq.net/yosys/nogit/vloghammer_tb.tar.bz2 tar --strip=1 -xjf vloghammer_tb.tar.bz2 make clean |