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author | Clifford Wolf <clifford@clifford.at> | 2019-11-19 17:29:27 +0100 |
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committer | GitHub <noreply@github.com> | 2019-11-19 17:29:27 +0100 |
commit | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (patch) | |
tree | 7825f438b83fdc730764ba15016eeeac9eb0cf41 /tests/arch/gowin/adffs.ys | |
parent | 15232a48af60fb7da3c3afdd144882ace2194197 (diff) | |
parent | 8ab412eb16b1d4f98117247bf85e0c37627ee459 (diff) | |
download | yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.tar.gz yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.tar.bz2 yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.zip |
Merge pull request #1449 from pepijndevos/gowin
Improvements for gowin support
Diffstat (limited to 'tests/arch/gowin/adffs.ys')
-rw-r--r-- | tests/arch/gowin/adffs.ys | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/tests/arch/gowin/adffs.ys b/tests/arch/gowin/adffs.ys new file mode 100644 index 000000000..fc7ee01f2 --- /dev/null +++ b/tests/arch/gowin/adffs.ys @@ -0,0 +1,55 @@ +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +stat +select -assert-count 1 t:DFFC +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFC +select -assert-count 1 t:LUT1 +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFS +select -assert-count 4 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFNR +select -assert-count 1 t:LUT1 +select -assert-count 4 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D |