From 83fbfe0964dc7315ca6d508e6069507250d9f093 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 21 Oct 2019 16:25:15 +0200
Subject: Add some tests

Copied from Efinix.

* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
---
 tests/arch/gowin/adffs.ys | 55 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 tests/arch/gowin/adffs.ys

(limited to 'tests/arch/gowin/adffs.ys')

diff --git a/tests/arch/gowin/adffs.ys b/tests/arch/gowin/adffs.ys
new file mode 100644
index 000000000..fc7ee01f2
--- /dev/null
+++ b/tests/arch/gowin/adffs.ys
@@ -0,0 +1,55 @@
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+stat
+select -assert-count 1 t:DFFC
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFC
+select -assert-count 1 t:LUT1
+select -assert-count 3 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFS
+select -assert-count 4 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:DFFNR
+select -assert-count 1 t:LUT1
+select -assert-count 4 t:IBUF
+select -assert-count 1 t:OBUF
+
+select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D
-- 
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