Share common tests

17 files changed, 19 insertions, 221 deletions

diff --git a/tests/arch/anlogic/add_sub.v b/tests/arch/anlogic/add_sub.v
deleted file mode 100644
index 177c32e30..000000000
--- a/tests/arch/anlogic/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys
index b8b67cc46..5396ce7ec 100644
--- a/tests/arch/anlogic/add_sub.ys
+++ b/tests/arch/anlogic/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
diff --git a/tests/arch/anlogic/counter.v b/tests/arch/anlogic/counter.v
deleted file mode 100644
index 52852f8ac..000000000
--- a/tests/arch/anlogic/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (

-out,

-clk,

-reset

-);

-    output [7:0] out;

-    input clk, reset;

-    reg [7:0] out;

-

-    always @(posedge clk, posedge reset)

-		if (reset) begin

-			out <= 8'b0 ;

-		end else

-			out <= out + 1;

-

-

-endmodule

diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys
index 036fdba46..d363ec24e 100644
--- a/tests/arch/anlogic/counter.ys
+++ b/tests/arch/anlogic/counter.ys
@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/arch/anlogic/dffs.v b/tests/arch/anlogic/dffs.v
deleted file mode 100644
index 3418787c9..000000000
--- a/tests/arch/anlogic/dffs.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys
index 9cbe5fce7..d3281ab89 100644
--- a/tests/arch/anlogic/dffs.ys
+++ b/tests/arch/anlogic/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/arch/anlogic/fsm.v b/tests/arch/anlogic/fsm.v
deleted file mode 100644
index 368fbaace..000000000
--- a/tests/arch/anlogic/fsm.v
+++ /dev/null
@@ -1,55 +0,0 @@
- module fsm (

- clock,

- reset,

- req_0,

- req_1,

- gnt_0,

- gnt_1

- );

- input   clock,reset,req_0,req_1;

- output  gnt_0,gnt_1;

- wire    clock,reset,req_0,req_1;

- reg     gnt_0,gnt_1;

-

- parameter SIZE = 3           ;

- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;

-

- reg [SIZE-1:0] state;

- reg [SIZE-1:0] next_state;

-

- always @ (posedge clock)

- begin : FSM

- if (reset == 1'b1) begin

-   state <=  #1  IDLE;

-   gnt_0 <= 0;

-   gnt_1 <= 0;

- end else

-  case(state)

-    IDLE : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-                 gnt_0 <= 1;

-               end else if (req_1 == 1'b1) begin

-                 gnt_1 <= 1;

-                 state <=  #1  GNT0;

-               end else begin

-                 state <=  #1  IDLE;

-               end

-    GNT0 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-               end else begin

-                 gnt_0 <= 0;

-                 state <=  #1  IDLE;

-               end

-    GNT1 : if (req_1 == 1'b1) begin

-                 state <=  #1  GNT2;

-				 gnt_1 <= req_0;

-               end

-    GNT2 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT1;

-				 gnt_1 <= req_1;

-               end

-    default : state <=  #1  IDLE;

- endcase

- end

-

-endmodule

diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
index 452ef9251..f45951b13 100644
--- a/tests/arch/anlogic/fsm.ys
+++ b/tests/arch/anlogic/fsm.ys
@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 #flatten
diff --git a/tests/arch/anlogic/latches.v b/tests/arch/anlogic/latches.v
deleted file mode 100644
index adb5d5319..000000000
--- a/tests/arch/anlogic/latches.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys
index c00c7a25d..8d66f77b3 100644
--- a/tests/arch/anlogic/latches.ys
+++ b/tests/arch/anlogic/latches.ys
@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/tests/arch/anlogic/logic.ys b/tests/arch/anlogic/logic.ys
new file mode 100644
index 000000000..125ee5d0f
--- /dev/null
+++ b/tests/arch/anlogic/logic.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:AL_MAP_LUT1
+select -assert-count 6 t:AL_MAP_LUT2
+select -assert-count 2 t:AL_MAP_LUT4
+select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D
diff --git a/tests/arch/anlogic/mux.v b/tests/arch/anlogic/mux.v
deleted file mode 100644
index 27bc0bf0b..000000000
--- a/tests/arch/anlogic/mux.v
+++ /dev/null
@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys
index 64ed2a2bd..3d5fe7c9a 100644
--- a/tests/arch/anlogic/mux.ys
+++ b/tests/arch/anlogic/mux.ys
@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2
diff --git a/tests/arch/anlogic/shifter.v b/tests/arch/anlogic/shifter.v
deleted file mode 100644
index 04ae49d83..000000000
--- a/tests/arch/anlogic/shifter.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module top    (

-out,

-clk,

-in

-);

-    output [7:0] out;

-    input signed clk, in;

-    reg signed [7:0] out = 0;

-

-    always @(posedge clk)

-	begin

-		out    <= out >> 1;

-		out[7] <= in;

-	end

-

-endmodule

diff --git a/tests/arch/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys
index 5eaed30a3..12df44b2a 100644
--- a/tests/arch/anlogic/shifter.ys
+++ b/tests/arch/anlogic/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/arch/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v
deleted file mode 100644
index 90dd314e4..000000000
--- a/tests/arch/anlogic/tribuf.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
diff --git a/tests/arch/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys
index 0eb1338ac..eaa073750 100644
--- a/tests/arch/anlogic/tribuf.ys
+++ b/tests/arch/anlogic/tribuf.ys
@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten