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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 22:33:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 22:33:35 -0700 |
| commit | f984e0cb345c7cec85eb9b90a13faacffa2e3fa2 (patch) | |
| tree | 461629a0ef6922aeec6dcf377e158e0d28086cae /techlibs | |
| parent | 375fcbe5113db80a92b950e5aca7df17add67acf (diff) | |
| download | yosys-f984e0cb345c7cec85eb9b90a13faacffa2e3fa2.tar.gz yosys-f984e0cb345c7cec85eb9b90a13faacffa2e3fa2.tar.bz2 yosys-f984e0cb345c7cec85eb9b90a13faacffa2e3fa2.zip | |
Another typo
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 8e0b578ab..e4937f646 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -112,7 +112,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q)); endgenerate endmodule -module FDPE_1 (output reg Q, input C, CE, D, CLR); +module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; wire \$nextQ , \$currQ ; \$__ABC_FDPE_1 #( |