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-rw-r--r--techlibs/xilinx/abc_ff.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 8e0b578ab..e4937f646 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -112,7 +112,7 @@ module FDPE (output reg Q, input C, CE, D, PRE);
\$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
endgenerate
endmodule
-module FDPE_1 (output reg Q, input C, CE, D, CLR);
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ;
\$__ABC_FDPE_1 #(