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| author | clairexen <claire@symbioticeda.com> | 2020-07-16 18:30:50 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-16 18:30:50 +0200 |
| commit | f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af (patch) | |
| tree | d1df653eb303ad71b4d9ecc4ac5550eb61d52c52 /techlibs | |
| parent | c49344b262b455bf03239a5bc7453f0706cc45d8 (diff) | |
| parent | 128522f1737fc45dcc107381a167e59a79a48595 (diff) | |
| download | yosys-f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af.tar.gz yosys-f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af.tar.bz2 yosys-f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af.zip | |
Merge pull request #2273 from whitequark/write-verilog-always-star-initial
verilog_backend: in non-SV mode, add a trigger for `always @*`
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions