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| author | clairexen <claire@symbioticeda.com> | 2020-07-16 18:30:50 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-16 18:30:50 +0200 |
| commit | f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af (patch) | |
| tree | d1df653eb303ad71b4d9ecc4ac5550eb61d52c52 | |
| parent | c49344b262b455bf03239a5bc7453f0706cc45d8 (diff) | |
| parent | 128522f1737fc45dcc107381a167e59a79a48595 (diff) | |
| download | yosys-f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af.tar.gz yosys-f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af.tar.bz2 yosys-f3d7e9a1df9cef87f51c8f5a8fb0b4f47ddcb2af.zip | |
Merge pull request #2273 from whitequark/write-verilog-always-star-initial
verilog_backend: in non-SV mode, add a trigger for `always @*`
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e174a6ea4..71f71554b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1718,6 +1718,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo } f << stringf("%s" "always%s begin\n", indent.c_str(), systemverilog ? "_comb" : " @*"); + if (!systemverilog) + f << indent + " " << "if (" << id("\\initial") << ") begin end\n"; dump_case_body(f, indent, &proc->root_case, true); std::string backup_indent = indent; @@ -1850,6 +1852,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } f << stringf(");\n"); + if (!systemverilog && !module->processes.empty()) + f << indent + " " << "reg " << id("\\initial") << " = 0;\n"; + for (auto w : module->wires()) dump_wire(f, indent + " ", w); |