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-rw-r--r--techlibs/common/mul2dsp.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 37ce2e485..ece45db79 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -227,7 +227,7 @@ module \$__mul_gen (A, B, Y);
if (Y_WIDTH < A_WIDTH+B_WIDTH)
assign Y = out[Y_WIDTH-1:0];
else begin
- wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+BWIDTH-1] : 1'b0);
+ wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+B_WIDTH-1] : 1'b0);
assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] };
end
end