From d4a1b0af5b41d1360c74a73fb2ae92ee5f6c3bd0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 31 Mar 2014 14:14:40 +0200
Subject: Added support for dlatchsr cells

---
 techlibs/common/simcells.v | 104 +++++++++++++++++++++++++++++++++++++++++++++
 techlibs/common/simlib.v   |  32 ++++++++++++++
 2 files changed, 136 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 10a809db6..5ecec7891 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -325,3 +325,107 @@ always @* begin
 end
 endmodule
 
+module  \$_DLATCHSR_NNN_ (E, S, R, D, Q);
+input E, S, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+module  \$_DLATCHSR_NNP_ (E, S, R, D, Q);
+input E, S, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+module  \$_DLATCHSR_NPN_ (E, S, R, D, Q);
+input E, S, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+module  \$_DLATCHSR_NPP_ (E, S, R, D, Q);
+input E, S, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+module  \$_DLATCHSR_PNN_ (E, S, R, D, Q);
+input E, S, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+module  \$_DLATCHSR_PNP_ (E, S, R, D, Q);
+input E, S, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+module  \$_DLATCHSR_PPN_ (E, S, R, D, Q);
+input E, S, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+module  \$_DLATCHSR_PPP_ (E, S, R, D, Q);
+input E, S, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 4436abfe7..908314f84 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1097,6 +1097,38 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$dlatchsr (EN, SET, CLR, D, Q);
+
+parameter WIDTH = 0;
+parameter EN_POLARITY = 1'b1;
+parameter SET_POLARITY = 1'b1;
+parameter CLR_POLARITY = 1'b1;
+
+input EN;
+input [WIDTH-1:0] SET, CLR, D;
+output reg [WIDTH-1:0] Q;
+
+wire pos_en = EN == EN_POLARITY;
+wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
+wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
+
+genvar i;
+generate
+	for (i = 0; i < WIDTH; i = i+1) begin:bit
+		always @*
+			if (pos_clr[i])
+				Q[i] <= 0;
+			else if (pos_set[i])
+				Q[i] <= 1;
+			else if (pos_en)
+				Q[i] <= D[i];
+	end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
 
 parameter NAME = "";
-- 
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