diff options
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 32 |
1 files changed, 20 insertions, 12 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 2c4d2f462..8d93a4a33 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -24,7 +24,8 @@ module FACADE_FF #( parameter LSRMUX = "LSR", parameter LSRONMUX = "LSRMUX", parameter SRMODE = "LSR_OVER_CE", - parameter REGSET = "SET" + parameter REGSET = "SET", + parameter REGMODE = "FF" ) ( input CLK, DI, LSR, CE, output reg Q @@ -41,22 +42,29 @@ module FACADE_FF #( endgenerate wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; + wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; generate - if (SRMODE == "ASYNC") begin - always @(posedge muxclk, posedge muxlsr) - if (muxlsr) - Q <= srval; - else if (muxce) - Q <= DI; + if (REGMODE == "FF") begin + if (SRMODE == "ASYNC") begin + always @(posedge muxclk, posedge muxlsron) + if (muxlsron) + Q <= srval; + else if (muxce) + Q <= DI; + end else begin + always @(posedge muxclk) + if (muxlsron) + Q <= srval; + else if (muxce) + Q <= DI; + end + end else if (REGMODE == "LATCH") begin + ERROR_UNSUPPORTED_FF_MODE error(); end else begin - always @(posedge muxclk) - if (muxlsr) - Q <= srval; - else if (muxce) - Q <= DI; + ERROR_UNKNOWN_FF_MODE error(); end endgenerate endmodule |