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author | Clifford Wolf <clifford@clifford.at> | 2017-10-07 13:40:54 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-10-07 13:40:54 +0200 |
commit | adf17547290b403e863ed7c71960a5678c6bbfaf (patch) | |
tree | fbc4a1c5cba91aa23ea455e6dfe002f6db668a3b /techlibs | |
parent | 2b04e8caa6043c309cf596ee21e55541b2e2b24c (diff) | |
download | yosys-adf17547290b403e863ed7c71960a5678c6bbfaf.tar.gz yosys-adf17547290b403e863ed7c71960a5678c6bbfaf.tar.bz2 yosys-adf17547290b403e863ed7c71960a5678c6bbfaf.zip |
Add $shiftx support to verilog front-end
Diffstat (limited to 'techlibs')
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