From acb341745d436987ad764c9198ff0c6ab63c572c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 14 Mar 2020 14:33:44 +0100 Subject: Fix invalid verilog syntax --- techlibs/common/gate2lut.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'techlibs') diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v index 99c123f4a..15cea3d8d 100644 --- a/techlibs/common/gate2lut.v +++ b/techlibs/common/gate2lut.v @@ -79,7 +79,7 @@ module _90_lut_mux (A, B, S, Y); // A 1010 1010 // B 1100 1100 // S 1111 0000 - .LUT(8'b_1100_1010) + .LUT(8'b 1100_1010) ) lut ( .A(AA), .Y(Y) -- cgit v1.2.3