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-rw-r--r--techlibs/common/simlib.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 493292582..342555024 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1340,7 +1340,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
- for (i = 0; i < WIDTH; i = i+1) begin:bit
+ for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @(posedge pos_set[i], posedge pos_clr[i])
if (pos_clr[i])
Q[i] <= 0;
@@ -1409,7 +1409,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
- for (i = 0; i < WIDTH; i = i+1) begin:bit
+ for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
if (pos_clr[i])
Q[i] <= 0;
@@ -1485,7 +1485,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
- for (i = 0; i < WIDTH; i = i+1) begin:bit
+ for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @*
if (pos_clr[i])
Q[i] = 0;