diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-04 14:34:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-04 14:34:36 -0700 |
| commit | 94a5f4e60985fc1e3fea75eec85638fa29874bea (patch) | |
| tree | cfcb9f7d9992049741b7051937119e69d9e8b29b /techlibs | |
| parent | 7b186740d33972612cfc9f2ebe31258edb0cca2b (diff) | |
| download | yosys-94a5f4e60985fc1e3fea75eec85638fa29874bea.tar.gz yosys-94a5f4e60985fc1e3fea75eec85638fa29874bea.tar.bz2 yosys-94a5f4e60985fc1e3fea75eec85638fa29874bea.zip | |
Rename shregmap -tech xilinx -> xilinx_dynamic
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e9eccfc0e..b2559d272 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -263,8 +263,8 @@ struct SynthXilinxPass : public ScriptPass // shregmap operates on bit-level flops, not word-level, // so break those down here run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')"); - // shregmap with '-tech xilinx' infers variable length shift regs - run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); + // shregmap to infer variable length shift regs + run("shregmap -tech xilinx_dynamic -minlen 3", "(skip if '-nosrl')"); } std::string techmap_files = " -map +/techmap.v"; |