From 65f91e51205fdd436c569c4795517160960ac700 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 3 Oct 2017 17:31:21 +0200 Subject: Rename "write_verilog -nobasenradix" to "write_verilog -decimal" --- techlibs/intel/synth_intel.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'techlibs') diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 4c4c13016..5f8b9c92a 100755 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -63,9 +63,6 @@ struct SynthIntelPass : public ScriptPass { log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); - log(" -nobasenradix\n"); - log(" dump the VQM netlist in clearbox format for certain defparam primitives\n"); - log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); @@ -232,7 +229,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("vqm")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -attr2comment -defparam -nohex -nobasenradix -renameprefix syn_ %s", + run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s", help_mode ? "" : vout_file.c_str())); } } -- cgit v1.2.3