From 28bf712372c494043c7adc0de904925a9199c939 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 6 Jan 2020 11:55:56 -0800
Subject: Wrap arrival functions inside `YOSYS too

---
 techlibs/xilinx/cells_sim.v | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'techlibs')

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 5e4529fd6..1cd4d2f30 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -2241,6 +2241,7 @@ module DSP48E1 (
     parameter [4:0] IS_INMODE_INVERTED = 5'b0;
     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 
+`ifdef YOSYS
     function integer \DSP48E1.P_arrival ;
     begin
         \DSP48E1.P_arrival = 0;
@@ -2309,6 +2310,7 @@ module DSP48E1 (
         //    $error("Invalid DSP48E1 configuration");
     end
     endfunction
+`endif
 
     initial begin
 `ifndef YOSYS
-- 
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