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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-18 10:52:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-18 10:52:07 +0200 |
| commit | 93d99559ef940193a77d132fc52449259484aa1a (patch) | |
| tree | 77d0970c9bc56b0b04137cd50eaaf731e5d1fb1c /techlibs | |
| parent | 22d9535a2481ffa7e05b0669bb1dc97284abf9d7 (diff) | |
| parent | 097da32e1a8cfe29d64666c1b2c9b47129b07c7e (diff) | |
| download | yosys-93d99559ef940193a77d132fc52449259484aa1a.tar.gz yosys-93d99559ef940193a77d132fc52449259484aa1a.tar.bz2 yosys-93d99559ef940193a77d132fc52449259484aa1a.zip | |
Merge pull request #664 from tklam/ignore-verilog-protect
Ignore protect endprotect
Diffstat (limited to 'techlibs')
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