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| author | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-22 20:43:39 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-22 20:51:14 +0100 |
| commit | 666c6128a90de588ab26c876a257ea48edfded30 (patch) | |
| tree | 15ba522dc933438e1fb976a6e04757ab1a967bdd /techlibs/xilinx/xc3sda_dsp_map.v | |
| parent | aa1adb0f1e43c353356a8283ad1f2fc007d9f54b (diff) | |
| download | yosys-666c6128a90de588ab26c876a257ea48edfded30.tar.gz yosys-666c6128a90de588ab26c876a257ea48edfded30.tar.bz2 yosys-666c6128a90de588ab26c876a257ea48edfded30.zip | |
xilinx_dsp: Initial DSP48A/DSP48A1 support.
Diffstat (limited to 'techlibs/xilinx/xc3sda_dsp_map.v')
| -rw-r--r-- | techlibs/xilinx/xc3sda_dsp_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/xc3sda_dsp_map.v b/techlibs/xilinx/xc3sda_dsp_map.v index 87348a173..258f90395 100644 --- a/techlibs/xilinx/xc3sda_dsp_map.v +++ b/techlibs/xilinx/xc3sda_dsp_map.v @@ -27,7 +27,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .D(18'b0), .P(P_48), - .OPMODE(8'b0000010) + .OPMODE(8'b0000001) ); assign Y = P_48; endmodule |