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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 14:56:08 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-20 14:56:08 -0800 |
| commit | aa1adb0f1e43c353356a8283ad1f2fc007d9f54b (patch) | |
| tree | d4459dd2b19f98cb309278430b366839ca83e227 /techlibs/xilinx/xc3sda_dsp_map.v | |
| parent | 5986a4df40a9c19171624c772b39e4c003e9c6ff (diff) | |
| parent | a75e08c7094d7d6f623057ad936c63551f1ebfbe (diff) | |
| download | yosys-aa1adb0f1e43c353356a8283ad1f2fc007d9f54b.tar.gz yosys-aa1adb0f1e43c353356a8283ad1f2fc007d9f54b.tar.bz2 yosys-aa1adb0f1e43c353356a8283ad1f2fc007d9f54b.zip | |
Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
write_xaiger: only instantiate each whitebox cell type once
Diffstat (limited to 'techlibs/xilinx/xc3sda_dsp_map.v')
0 files changed, 0 insertions, 0 deletions