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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 18:52:03 -0800 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 18:52:03 -0800 |
| commit | 50e0c835606a94c825079a63fc026c906c9985e0 (patch) | |
| tree | 4347fee988aa882b1b640df4fbd1abbf585c2bbf /techlibs/xilinx/lutrams_map.v | |
| parent | 037d1a03df20b9c445790728bb80e1818d1edafa (diff) | |
| download | yosys-50e0c835606a94c825079a63fc026c906c9985e0.tar.gz yosys-50e0c835606a94c825079a63fc026c906c9985e0.tar.bz2 yosys-50e0c835606a94c825079a63fc026c906c9985e0.zip | |
Fix RAM64M model to have 6 bit address bus
Diffstat (limited to 'techlibs/xilinx/lutrams_map.v')
0 files changed, 0 insertions, 0 deletions